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PSD834210MIT 数据表(PDF) 78 Page - STMicroelectronics |
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PSD834210MIT 数据表(HTML) 78 Page - STMicroelectronics |
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78 / 89 page  PSD834F2V 78/89 Table 50. Port A Peripheral Data Mode Read Timing Table 51. Port A Peripheral Data Mode Write Timing Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). 2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. 3. Any input used to select Port A Data Peripheral mode. 4. Data is already stable on Port A. 5. Data stable on ADIO pins to data on Port A. Symbol Parameter Conditions -10 -15 -20 Turbo Off Unit Min Max Min Max Min Max tAVQV–PA Address Valid to Data Valid (Note 3) 50 50 50 + 20 ns tSLQV–PA CSI Valid to Data Valid 37 45 50 + 20 ns tRLQV–PA RD to Data Valid (Notes 1,4) 37 40 45 ns RD to Data Valid 8031 Mode 45 45 50 ns tDVQV–PA Data In to Data Out Valid 38 40 45 ns tQXRH–PA RD Data Hold Time 0 0 0 ns tRLRH–PA RD Pulse Width (Note 1) 36 36 46 ns tRHQZ–PA RD to Data High-Z (Note 1) 36 40 45 ns Symbol Parameter Conditions -10 -15 -20 Unit Min Max Min Max Min Max tWLQV–PA WR to Data Propagation Delay (Note 2) 42 45 55 ns tDVQV–PA Data to Port A Data Propagation Delay (Note 5) 38 40 45 ns tWHQZ–PA WR Invalid to Port A Tri-state (Note 2) 33 33 35 ns |
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