PSD834210MIT datasheet(69/89 Pages) STMICROELECTRONICS

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PSD834F2V

Table 42. DC Characteristics

Note: 1. Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC .

2. CSI deselected or internal PD is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 32 for the PLD current calculation.

5. IOUT = 0 mA

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VIH

High Level Input Voltage

3.0 V < VCC < 3.6 V

0.7VCC

VCC +0.5

VIL

Low Level Input Voltage

3.0 V < VCC < 3.6 V

–0.5

0.8

VIH1

Reset High Level Input Voltage

(Note 1)

0.8VCC

VCC +0.5

VIL1

Reset Low Level Input Voltage

(Note 1)

–0.5

0.2VCC –0.1

VHYS

Reset Pin Hysteresis

0.3

VLKO

VCC (min) for Flash Erase and

Program

1.5

2.2

VOL

Output Low Voltage

IOL = 20 µA, VCC = 3.0 V

0.01

0.1

IOL = 4 mA, VCC = 3.0 V

0.15

0.45

VOH

Output High Voltage Except

VSTBY On

IOH = –20 µA, VCC = 3.0 V

2.9

2.99

IOH = –1 mA, VCC = 3.0 V

2.7

2.8

VOH1

Output High Voltage VSTBY On

IOH1 = 1 µA

VSTBY – 0.8

VSTBY

SRAM Stand-by Voltage

2.0

VCC

ISTBY

SRAM Stand-by Current

VCC = 0 V

0.5

µA

IIDLE

Idle Current (VSTBY input)

VCC > VSTBY

–0.1

0.1

µA

VDF

SRAM Data Retention Voltage

Only on VSTBY

ISB

Stand-by Supply Current

for Power-down Mode

CSI >VCC –0.3 V (Notes

2,3)

100

µA

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±0.1

µA

ILO

Output Leakage Current

0.45 < VIN < VCC

–10

±5

µA

ICC (DC)

(Note 5)

Operating

Supply

Current

PLD Only

PLD_TURBO = Off,

f = 0 MHz (Note 3)

µA/PT

PLD_TURBO = On,

f = 0 MHz

200

400

µA/PT

Flash memory

During Flash memory Write/

Erase Only

Read Only, f = 0 MHz

SRAM

f = 0 MHz

ICC (AC)

(Note 5)

PLD AC Adder

note 4

Flash memory AC Adder

1.5

2.0

mA/

MHz

SRAM AC Adder

0.8

1.5

mA/

MHz

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