PSD834210MIT datasheet(23/89 Pages) STMICROELECTRONICS

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PSD834F2V

Reset Flash. The Reset Flash instruction con-

sists of one Write cycle (see Table 7). It can also

be optionally preceded by the standard two write

decoding cycles (writing AAh to 555h and 55h to

AAAh). It must be executed after:

– Reading the Flash Protection Status or Flash ID

– An Error condition has occurred (and the device

has set the Error Flag (DQ5) bit to 1) during a

Flash memory Program or Erase cycle.

The Reset Flash instruction puts the Flash memo-

ry back into normal Read mode. If an Error condi-

tion has occurred (and the device has set the Error

Flag (DQ5) bit to 1) the Flash memory is put back

into normal Read mode within 25

µs of the Reset

Flash instruction having been issued. The Reset

Flash instruction is ignored when it is issued dur-

ing a Program or Bulk Erase cycle of the Flash

memory. The Reset Flash instruction aborts any

on-going Sector Erase cycle, and returns the

Flash memory to the normal Read mode within

µs.

Reset (RESET) Signal. A pulse on Reset (RE-

SET) aborts any cycle that is in progress, and re-

sets the Flash memory to the Read mode. When

the reset occurs during a Program or Erase cycle,

the Flash memory takes up to 25

µs to return to

the Read mode. It is recommended that the Reset

(RESET) pulse (except for Power On Reset, as

described on page 60) be at least 25

µs so that the

Flash memory is always ready for the MCU to

fetch the bootstrap instructions after the Reset cy-

cle is complete.

SRAM

The SRAM is enabled when SRAM Select (RS0)

from the DPLD is High. SRAM Select (RS0) can

contain up to two product terms, allowing flexible

memory mapping.

The SRAM can be backed up using an external

battery. The external battery should be connected

to Voltage Stand-by (VSTBY, PC2). If you have an

external battery connected to the PSD, the con-

tents of the SRAM are retained in the event of a

power loss. The contents of the SRAM are re-

tained so long as the battery voltage remains at

2 V or greater. If the supply voltage falls below the

battery voltage, an internal power switch-over to

the battery occurs.

PC4 can be configured as an output that indicates

when power is being drawn from the external bat-

tery. Battery-on Indicator (VBATON, PC4) is High

with the supply voltage falls below the battery volt-

age and the battery on Voltage Stand-by (VSTBY,

PC2) is supplying power to the internal SRAM.

SRAM Select (RS0), Voltage Stand-by (VSTBY,

PC2) and Battery-on Indicator (VBATON, PC4)

are all configured using PSDsoft Express Configu-

ration.

Sector Select and SRAM Select

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)

and SRAM Select (RS0) are all outputs of the

DPLD. They are setup by writing equations for

them in PSDabel. The following rules apply to the

equations for these signals:

1. Primary Flash memory and secondary Flash

memory Sector Select signals must

not be larg-

er than the physical sector size.

2. Any primary Flash memory sector must

not be

mapped in the same memory space as another

Flash memory sector.

3. A secondary Flash memory sector must

not be

mapped in the same memory space as another

secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must

not

overlap.

5. A secondary Flash memory sector

may overlap

a primary Flash memory sector. In case of over-

lap, priority is given to the secondary Flash

memory sector.

6. SRAM, I/O, and Peripheral I/O spaces

may

overlap any other memory sector. Priority is giv-

en to the SRAM, I/O, or Peripheral I/O.

Example. FS0 is valid when the address is in the

range of 8000h to BFFFh, CSBOOT0 is valid from

8000h to 9FFFh, and RS0 is valid from 8000h to

87FFh. Any address in the range of RS0 always

accesses the SRAM. Any address in the range of

CSBOOT0 greater than 87FFh (and less than

9FFFh) automatically addresses secondary Flash

memory segment 0. Any address greater than

9FFFh accesses the primary Flash memory seg-

ment 0. You can see that half of the primary Flash

memory segment 0 and one-fourth of secondary

Flash memory segment 0 cannot be accessed in

this example. Also note that an equation that de-

fined FS1 to anywhere in the range of 8000h to

BFFFh would

not be valid.

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