PSD834210MIT datasheet(14/89 Pages) STMICROELECTRONICS

14 / 89 page

PSD834F2V

14/89

Table 5. I/O Port Latched Address Output Assignments1

Note: 1. See the section entitled “I/O Ports”, on page 45, on how to enable the Latched Address Output function.

2. N/A = Not Applicable

Table 6. Register Address Offset

Note: 1. Other registers that are not part of the I/O ports.

MCU

Port A

Port B

Port A (3:0)

Port A (7:4)

Port B (3:0)

Port B (7:4)

8051XA (8-bit)

N/A

Address a7-a4

Address a11-a8

N/A

80C251 (page mode)

N/A

Address a11-a8

Address a15-a12

All other 8-bit multiplexed

Address a3-a0

Address a7-a4

Address a3-a0

Address a7-a4

8-bit non-multiplexed bus

N/A

Address a3-a0

Address a7-a4

Port A

Port B

Port C

Port D

Other1

Description

Data In

Reads Port pin as input, MCU I/O input mode

Control

Selects mode between MCU I/O or Address Out

Data Out

Stores data for output to Port pins, MCU I/O output

mode

Direction

Configures Port pin as input or output

Drive Select

Configures Port pins as either CMOS or Open

Drain on some pins, while selecting high slew rate

on other pins.

Input Macrocell

Reads Input Macrocells

Enable Out

Reads the status of the output enable to the I/O

Port driver

Output Macrocells

Read – reads output of macrocells AB

Write – loads macrocell flip-flops

Output Macrocells

Read – reads output of macrocells BC

Write – loads macrocell flip-flops

Mask Macrocells AB

Blocks writing to the Output Macrocells AB

Mask Macrocells BC

Blocks writing to the Output Macrocells BC

Primary Flash

Protection

Read only – Primary Flash Sector Protection

Secondary Flash

memory Protection

Read only – PSD Security and Secondary Flash

memory Sector Protection

JTAG Enable

Enables JTAG Port

PMMR0

Power Management Register 0

PMMR2

Power Management Register 2

Page

Page Register

Places PSD memory areas in Program and/or

Data space on an individual basis.

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