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PSD834210MIT 数据表(PDF) 80 Page - STMicroelectronics

部件名 PSD834210MIT
功能描述  Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  89 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD834210MIT 数据表(HTML) 80 Page - STMicroelectronics

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Table 52. Reset (Reset) Timing
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.
Table 53. VSTBYON Timing
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Table 54. ISC Timing
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Symbol
Parameter
Conditions
Min
Max
Unit
tNLNH
RESET Active Low Time 1
300
ns
tNLNH–PO
Power On Reset Active Low Time
1
ms
tNLNH–A
Warm Reset 2
25
µs
tOPR
RESET High to Operational Device
300
ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBYON Output High
(Note 1)
20
µs
tBXBL
VSTBY Off Detection to VSTBYON Output
Low
(Note 1)
20
µs
Symbol
Parameter
Conditions
-10
-15
-20
Unit
Min
Max
Min
Max
Min
Max
tISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note 1)
12
10
9
MHz
tISCCH
Clock (TCK, PC1) High Time (except for
PLD)
(Note 1)
40
45
51
ns
tISCCL
Clock (TCK, PC1) Low Time (except for
PLD)
(Note 1)
40
45
51
ns
tISCCFP
Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
222
MHz
tISCCHP
Clock (TCK, PC1) High Time (PLD only)
(Note 2)
240
240
240
ns
tISCCLP
Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
240
240
240
ns
tISCPSU
ISC Port Set Up Time
12
13
15
ns
tISCPH
ISC Port Hold Up Time
5
5
5
ns
tISCPCO
ISC Port Clock to Output
30
36
40
ns
tISCPZV
ISC Port High-Impedance to Valid Output
30
36
40
ns
tISCPVZ
ISC Port Valid Output to
High-Impedance
30
36
40
ns



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