PSD834210MIT datasheet(29/89 Pages) STMICROELECTRONICS

部件名	PSD834210MIT

功能描述	Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM

PDF	89 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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29 / 89 page

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PSD834F2V

Decode PLD (DPLD)

The DPLD, shown in Figure 11, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms

each)

4 Sector Select (CSBOOT0-CSBOOT3) signals

for the secondary Flash memory (three product

terms each)

1 internal SRAM Select (RS0) signal (two

product terms)

1 internal CSIOP Select (PSD Configuration

1 JTAG Select signal (enables JTAG on Port C)

2 internal Peripheral Select signals

(Peripheral I/O mode).

Figure 11. DPLD Logic Array

(INPUTS)

(24)

(8)

(16)

(1)

PDN (APD OUTPUT)

I /O PORTS (PORT A,B,C)

(8)

PGR0 - PGR7

(8)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

A[15:0]

(3)

PD[2:0] (ALE,CLKIN,CSI)

CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)

(1)

RESET

RD_BSY

RS0

CSIOP

PSEL0

PSEL1

8 PRIMARY FLASH

MEMORY SECTOR SELECTS

SRAM SELECT

I/O DECODER

SELECT

PERIPHERAL I/O MODE

SELECT

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

FS0

FS7

JTAGSEL

AI02873D

FS1

FS2

FS3

FS6

FS5

FS4

PSD834210MIT 数据表(PDF) 29 Page - STMicroelectronics

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