PSD834210MIT datasheet(26/89 Pages) STMICROELECTRONICS

部件名	PSD834210MIT

功能描述	Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM

PDF	89 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

26 / 89 page

PSD834F2V

26/89

Page Register

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included

the

Sector

Select

(FS0-FS7,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all 8 page

these bits may be used in the CPLD for general

logic. See Application Note

AN1154.

Figure 9 shows the Page Register. The eight flip-

flops in the register are connected to the internal

data bus D0-D7. The MCU can write to or read

from the Page Register. The Page Register can be

accessed at address location CSIOP + E0h.

Figure 9. Page Register

RESET

D 0-D 7

R/W

PAGE

PGR0

PGR1

PGR2

PGR3

DPLD

AND

CPLD

INTERNAL

SELECTS

AND LOGIC

PLD

PGR4

PGR5

PGR6

PGR7

AI02871B

PSD834210MIT 数据表(PDF) 26 Page - STMicroelectronics

PSD834210MIT 数据表(HTML) 26 Page - STMicroelectronics

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