ST10F280 datasheet(62/186 Pages) STMICROELECTRONICS

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ST10F280

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11.2.1 - Operating Modes

The XPWM module provides four different operat-

ing modes:

– Mode 0 Standard PWM generation (edge

aligned PWM) available on all four channels

– Mode 1 Symmetrical PWM generation (center

aligned PWM) available on all four channels

– Burst mode combines channels 0 and 1

– Single shot mode available on channels 2 and 3

Note: The output signals of the XPWM module

are

XORed

with

the

outputs

the

respective bits of XPOLAR register. After

reset these bits are cleared, so the PWM

signals are directly driven to the output pins.

By setting the respective bits of XPOLAR

inverted (XORed with ‘1’) before being

driven to the output pin. The descriptions

below refer to the standard case after reset,

i.e. direct driving.

11.2.1.1 - Mode 0: Standard PWM Generation

(Edge Aligned PWM)

Mode 0 is selected by clearing the respective bit

XPMx in register XPWMCON1 to ‘0’. In this mode

the timer XPTx of the respective XPWM channel

is always counting up until it reaches the value in

the associated period shadow register. Upon the

next count pulse the timer is reset to 0000h and

continues counting up with subsequent count

pulses. The XPWM output signal is switched to

high level when the timer contents are equal to or

greater than the contents of the pulse width

shadow register. The signal is switched back to

low level when the respective timer is reset to

0000h, i.e. below the pulse width shadow register.

The period of the resulting PWM signal is deter-

mined by the value of the respective XPPx

shadow register plus 1, counted in units of the

timer resolution.

PWM_PeriodMode0 = [XPPx] + 1

The duty cycle of the XPWM output signal is con-

trolled by the value in the respective pulse width

shadow register. This mechanism allows the

selection of duty cycles from 0% to 100% including

the boundaries. For a value of 0000h the output

will remain at a high level, representing a duty

cycle of 100%. For a value higher than the value in

the period register the output will remain at a low

level, which corresponds to a duty cycle of 0%.

The Figure 20 illustrates the operation and output

waveforms of a XPWM channel in mode 0 for dif-

ferent values in the pulse width register.

This mode is referred to as Edge Aligned PWM,

because the value in the pulse width (shadow)

put signal. The negative edge is always fixed and

related to the clearing of the timer.

Figure 20 : Operation and Output Waveform in Mode 0

XPPx

Period=7

XPTx Count

Value

XPWx Pulse

Width=0

XPWx=1

XPWx=2

XPWx=4

XPWx=6

XPWx=7

XPWx=8

Latch Shadow Registers

Interrupt Request

LSR

Duty Cycle

100%

87.5%

75%

50%

25%

12.5%

LSR

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