ST10F280 datasheet(55/186 Pages) STMICROELECTRONICS

55 / 186 page

ST10F280

55/186

Figure 13 : Block Diagram of CAPCOM Timers T0 and T7

Figure 14 : Block Diagram of CAPCOM Timers T1 and T8

Note: When

external

input

signal

connected to the input lines of both T0 and

T7, these timers count the input signal

synchronously. Thus the two timers can be

regarded as one timer whose contents can

be compared with 32 capture registers.

When a capture/compare register has been

selected for capture mode, the current contents of

the allocated timer will be latched (captured) into

the capture/compare register in response to an

external event at the port pin which is associated

with this register. In addition, a specific interrupt

request for this capture/compare register is

generated.

Either a positive, a negative, or both a positive

and a negative external signal transition at the pin

can be selected as the triggering event. The

contents of all registers which have been selected

for

one

the

five

compare

modes

are

continuously compared with the contents of the

allocated timers.

When a match occurs between the timer value

and the value in a capture /compare register,

specific actions will be taken based on the

selected compare mode (see Table 9).

The input frequencies fTx, for the timer input

selector Tx, are determined as a function of the

CPU

clocks.

The

timer

input

frequencies,

resolution and periods which result from the

selected pre-scaler option in TxI when using a

40MHz CPU clock are listed in the Table 10.

The numbers for the timer periods are based on a

reload value of 0000h. Note that some numbers

may be rounded to 3 significant figures.

Txl

CPU

Clock

TxR

MUX

GPT2 Timer T6

Over / Underflow

Edge Select

TxIN

Txl

Txl TxM

Input

Control

Reload Register TxREL

CAPCOM Timer Tx

TxIR

Interrupt

Request

x = 0, 7

Txl

CPU

Clock

TxR

MUX

GPT2 Timer T6

Over / Underflow

TxM

Reload Register TxREL

CAPCOM Timer Tx

TxIR

Interrupt

Request

x = 1, 8

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