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ST10F280 数据表(PDF) 17 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 186 page ![]() ST10F280 17/186 3 - FUNCTIONAL DESCRIPTION The architecture of the ST10F280 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth inter- nal bus structure of the ST10F280. Figure 3 : Block Diagram P4.7 CAN2_TxD P4.6 CAN1_TxD P4.5 CAN1_RxD P4.4 CAN2_RxD Port 6 Port 5 Port 3 BRG CPU-Core and MAC Unit Internal RAM Watchdog Interrupt Controller 8 32 16 PEC 16 16 CAN1 Port 7 Port 8 BRG 16 Oscillator 16 16 512K Byte and PLL Flash Memory XTAL1 XTAL2 2K Byte 15 8 8 8 16 3.3V Voltage Regulator 16K Byte XRAM CAN2 XPORT9 16 XPWM 4 XTIMER P7.7 Trigger for ADC 16 XPORT10 16 16 XADCINJ channel injection External connexion |
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