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ST10F280 数据表(PDF) 67 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 67 Page - STMicroelectronics |
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67 / 186 page  ST10F280 67/186 XPWM Control Registers Register XPWMCON0 controls the function of the timers of the four XPWM channels and the channel specific interrupts. Having the control bits organized in functional groups allows e.g. to start or stop all 4 XPWM timers simultaneously with one bitfield instruction. Note: This register is not bit-addressable. XPWMCON0 (EC00h) Reset Value: 0000h Register XPWMCON1 controls the operating modes and the outputs of the four XPWM channels. The basic operating mode for each channel (standard=edge aligned, or symmetrical=center aligned PWM mode) is selected by the mode bits XPMx. Burst mode (channels 0 and 1) and single shot mode (channel 2 or 3) are selected by separate control bits. The output signal of each XPWM channel is individually enabled by bit PENx. If the output is not enabled the respective pin can only be used to generate an inter- rupt request. Note: This register is not bit-addressable. XPWMCON1 (EC02h) Reset Value: 0000h 15 14 13 12 11 10 9876543210 PIR3 PIR2 PIR1 PIR0 PIE3 PIE2 PIE1 PIE0 PTI3 PTI2 PTI1 PTI0 PTR3 PTR2 PTR1 PTR0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Function PTRx 0 1 XPWM Timer x Run Control Bit Timer XPTx is disconnected from its input clock Timer XPTx is running PTIx 0 1 XPWM Timer x Input Clock Selection Timer XPTx clocked with CLKCPU TimerX PTx clocked with CLKCPU / 64 PIEx 0 1 XPWM Channel x Interrupt Enable Flag Interrupt from channel x disabled Interrupt from channel x enabled PIRx 0 1 XPWM Channel x Interrupt Request Flag No interrupt request from channel x Channel x interrupt pending (must be reset via software) 15 14 13 12 11 10 9876543210 PS3 PS2 - PB01 ---- PM3 PM2 PM1 PM0 PEN3 PEN2 PEN1 PEN0 RW RW - RW ---- RW RW RW RW RW RW RW RW Bit Function PENx 0 1 XPWM Channel x Output Enable Bit Channel x output signal disabled, generate interrupt only Channel x output signal enabled PMx 0 1 XPWM Channel x Mode Control Bit Channel x operates in mode 0, edge aligned PWM Channel x operates in mode 1, center aligned PWM PB01 0 1 XPWM Channel 0/1 Burst Mode Control Bit Channels 0 and 1 work independently in respective standard mode Outputs of channels 0 and 1 are ANDed to XPWM0 in burst mode PSx 0 1 XPWM Channel x Single Shot Mode Control Bit Channel x works in respective standard mode Channel x operates in single shot mode |
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