ST10F280 datasheet(29/186 Pages) STMICROELECTRONICS

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ST10F280

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– Generally, command sequences cannot be

written to Flash by instructions fetched from the

Flash itself. Thus, the Flash commands must be

written by instructions, executed from internal

RAM or external memory.

– Command cycles on the CPU interface need not

to be consecutively received (pauses allowed).

The CPU interface delivers dummy read data for

not used cycles within command sequences.

– All addresses of command cycles shall be

defined only with Register-indirect addressing

mode in the according move instructions. Direct

addressing

not

allowed

for

command

sequences. Address segment or data page

pointer are taken into account for the command

address value.

5.3.6 - Reset Processing and Initial State

The Flash module distinguishes two kinds of CPU

reset types

The lengthening of CPU reset:

– Is

not

reported

external

devices

bidirectional pin

– Is not enabled in case of external start of CPU

after reset.

5.4 - Flash Memory Configuration

The

default

memory

configuration

the

ST10F280 Memory is determined by the state of

the EA pin at reset. This value is stored in the

Internal ROM Enable bit (named ROMEN) of the

SYSCON register.

When ROMEN = 0, the internal Flash is disabled

and external ROM is used for startup control.

Flash memory can later be enabled by setting the

ROMEN

bit

SYSCON

The

code

performing this setting must not run from a

segment of the external ROM to be replaced by a

segment

the

Flash

memory,

otherwise

unexpected behaviour may occur.

For example, if external ROM code is located in

the first 32K Bytes of segment 0, the first

32K Bytes of the Flash must then be enabled in

segment 1. This is done by setting the ROMS1 bit

of SYSCON to 0 before or simultaneously with

setting of ROMEN bit. This must be done in the

externally supplied program before the execution

of the EINIT instruction.

If program execution starts from external memory,

but access to the Flash memory mapped in

segment 0 is later required, then the code that

performs the setting of ROMEN bit must be

executed either in the segment 0 but above

address 00’8000h, or from the internal RAM.

Bit ROMS1 only affects the mapping of the first

32K Bytes of the Flash memory. All other parts of

the

Flash

memory

(addresses

01’8000h

08’FFFFh) remain unaffected.

The SGTDIS Segmentation Disable / Enable must

also be set to 0 to allow the use of the full

512K Bytes of on-chip memory in addition to the

external boot memory. The correct procedure on

changing the segmentation registers must also be

observed to prevent an unwanted trap condition:

– Instructions that configure the internal memory

must only be executed from external memory or

from the internal RAM.

– An

Absolute

Inter-Segment

Jump

(JMPS)

instruction

must

executed

after

Flash

enabling, to the next instruction, even if this next

instruction is located in the consecutive address.

– Whenever the internal Memory is disabled,

enabled or remapped, the DPPs must be

explicitly (re)loaded to enable correct data

accesses to the internal memory and/or external

memory.

5.5 - Application Examples

5.5.1 - Handling of Flash Addresses

All command, Block, Data and register addresses

to the Flash have to be located within the active

Flash memory space. The active space is that

address range to which the physical Flash

addresses are mapped as defined by the user.

When using data page pointer (DPP) for block

addresses make sure that address bit A15 and

A14 of the block address are reflected in both

LSBs of the selected DPPS.

Note: - For Command Instructions, address bit

A14, A15, A16, A17 and A18 are don’t

care. This simplify a lot the application

software, because it minimize the use of

DPP registers when using

Command in

the Command Interface.

- Direct addressing is not allowed for

Command sequence operations to the

Flash. Only Register-indirect addressing

can be used for command, block or

write-data accesses.

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