ST10F280 datasheet(23/186 Pages) STMICROELECTRONICS

23 / 186 page

ST10F280

23/186

With the two possibilities for write protection whole

memory or block specific a flexible installation of

write protection is supported to protect the Flash

memory

parts

from

unauthorized

programming or erase accesses and to provide

virus-proof protection for all system code blocks.

All write protection also is enabled during boot

operation.

Power Supply, Reset

The Flash module uses a single power supply for

both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations from 5V supply.

Once a program or erase cycle has been com-

pleted, the device resets to the standard read

mode. At power-on, the Flash memory has a

setup phase of some microseconds (dependent

on the power supply ramp-up). During this phase,

Flash can not be read. Thus, if EA pin is high (exe-

cution will start from Flash memory), the CPU will

remains in reset state until the Flash can be

accessed.

5.3 - Architectural Description

The

Flash

module

distinguishes

two

basic

operating modes, the standard read mode and the

command mode. The initial state after power-on

and after reset is the standard read mode.

5.3.1 - Read Mode

The Flash module enters the standard operating

mode, the read mode:

– After Reset command

– After every completed erase operation

– After every completed programming operation

– After

every

other

completed

command

execution

– Few microseconds after a CPU-reset has

started

– After incorrect address and data values of

command sequences or writing them in an

improper sequence

– After incorrect write access to a read protected

Flash memory

The read mode remains active until the last

command of a command sequence is decoded

which starts directly a Flash array operation, such

as:

– erase one or several blocks

– program a word into Flash array

– protect / temporary unprotect a block.

In the standard read mode read accesses are

directly controlled by the Flash memory array,

delivering

32-bit

double

Word

from

the

addressed position. Read accesses are always

aligned to double Word boundaries. Thus, both

low order address bit A1 and A0 are not used in

the Flash array for read accesses. The high order

address bit A18/A17/A16 define the physical

64K Bytes segment being accessed within the

Flash array.

5.3.2 - Command Mode

Every operation besides standard read operations

is initiated by commands written to the Flash

command register. The addresses used for

command cycles define in conjunction with the

actual state the specific step within command

sequences. With the last command of a command

sequence, the Erase-Program Controller (EPC)

starts the execution of the command. The EPC

status is indicated during command execution by:

– The Status Register,

– The Ready/Busy signal.

5.3.3 - Flash Status Register

The Flash Status register is used to flag the status

of the Flash memory and the result of an

operation. This register can be accessed by Read

cycles

during

the

program-Erase

Controller

operations. The program or erase operation can

be controlled by data polling on bit FSB.7 of

Status Register, detection of Toggle on FSB.6 and

FSB.2, or Error on FSB.5 and Erase Timeout on

FSB.3 bit. Any read attempt in Flash during EPC

operation will automatically output these five bits.

The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6

and FSB.7. Other bit are reserved for future use

and should be masked.

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