ST10F280 datasheet(94/186 Pages) STMICROELECTRONICS

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ST10F280

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ODP6 (F1CEh / E7h)

ESFR

Reset Value: - - 00h

12.8.1 - Alternate Functions of Port 6

A programmable number of chip select signals (CS4...CS0) derived from the bus control registers

(BUSCON4...BUSCON0) can be output on the 5 pins of Port 6. The number of chip select signals is

selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H

(read only) e.g. in order to check the configuration during run time. The table below summarizes the alter-

nate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL).

Figure 44 : Port 6 I/O and Alternate Functions

Bit

Function

DP6.y

Port direction register DP6 bit y

DP6.y = 0: Port line P6.y is an input (high-impedance)

DP6.y = 1: Port line P6.y is an output

7654321

--------

ODP6.7ODP6.6ODP6.5 ODP6.4 ODP6.3 ODP6.2 ODP6.1 ODP6.0

Bit

Function

ODP6.y

Port 6 Open Drain control register bit y

ODP6.y = 0: Port line P6.y output driver in push/pull mode

ODP6.y = 1: Port line P6.y output driver in open drain mode

Table 18 : Port 6 Alternate Functions

Port 6 Pin

Altern. Function

CSSEL = 10

Altern. Function

CSSEL = 01

Altern. Function

CSSEL = 00

Altern. Function

CSSEL = 11

P6.0

P6.1

P6.2

P6.3

P6.4

General purpose I/O

Chip select CS0

Chip select CS1

Gen. purpose I/O

Chip select CS0

Chip select CS1

Chip select CS2

Gen. purpose I/O

Chip select CS0

Chip select CS1

Chip select CS2

Chip select CS3

Chip select CS4

P6.5

P6.6

P6.7

HOLD External hold request input

HLDA Hold acknowledge output

BREQ Bus request output

Port 6

Alternate Function

General Purpose Input/Output

P6.7

P6.6

P6.5

P6.4

P6.3

P6.2

P6.1

P6.0

BREQ

HLDA

HOLD

CS4

CS3

CS2

CS1

CS0

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