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ST10F280 数据表(PDF) 72 Page - STMicroelectronics

部件名 ST10F280
功能描述  16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F280 数据表(HTML) 72 Page - STMicroelectronics

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Figure 26 : XBUS Registers Associated with the Parallel Ports
12.1 - Introduction
12.1.1 - Open Drain Mode
In the ST10F280 some ports provide Open Drain
Control. This make is possible to switch the output
driver of a port pin from a push/pull configuration
to an open drain configuration. In push/pull mode
a port output driver has an upper and a lower tran-
sistor, thus it can actively drive the line either to a
high or a low level. In open drain mode the upper
transistor is always switched off, and the output
driver can only actively drive the line to a low level.
When writing a ‘1’ to the port latch, the lower tran-
sistor is switched off and the output enters a
high-impedance state. The high level must then
be provided by an external pull-up device. With
this feature, it is possible to connect several port
pins together to a Wired-AND configuration, sav-
ing external glue logic and/or additional software
overhead for enabling/disabling output signals.
This feature is implemented for ports P2, P3, P4,
P6, P7 and P8 (see respective sections), and is
controlled through the respective Open Drain
Control Registers ODPx. These registers allow
the individual bit-wise selection of the open drain
mode for each port line. If the respective control
bit ODPx.y is ‘0’ (default after reset), the output
driver is in the push/pull mode. If ODPx.y is ‘1’, the
open drain configuration is selected. Note that all
ODPx registers are located in the ESFR space.
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Y
XP9
YYYY Y Y YY YYYYYYYY
XP9SET
YYYY Y Y YY YYYYYYYY
XP9CLR
YYYY Y Y YY YYYYYYYY
XP10
YYYY Y Y YY YYYYYYYY
XP10DIDIS
----
-
-
-- ------- Y
XADCMUX
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Y
XDP9
YYYY Y Y YYYYYYY YYY
XP9SET
YYYY Y Y YYYYYYY YYY
XP9CLR
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Y
XOP9
YYYY Y Y YYY YYYYYYY
XOP9SET
YYYY Y Y YYY YYYYYYY
XOP9CLR
Figure 27 : Output Drivers in Push/Pull Mode and in Open Drain Mode
Pin
Q
Push-Pull Output Driver
Q
Open Drain Output Driver
External
Pullup
Pin



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