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ST10F280 数据表(PDF) 83 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 83 Page - STMicroelectronics |
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83 / 186 page ![]() ST10F280 83/186 The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Figure 34 : Block Diagram of a Port 2 Pin Open Drain Latch Write ODP2.y Read ODP2.y Direction Latch Write DP2.y Read DP2.y MUX 0 1 Alternate Data Input Input Latch P2.y CCyIO Output Buffer x = 7...0 Alternate Data Output MUX 0 1 Output Latch ≥ 1 Write Port P2.y Compare Trigger Read P2.y Fast External Interrupt Input CPU Clock EXxIN y = 15...0 |
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