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ST10F280 数据表(PDF) 76 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 186 page  ST10F280 76/186 On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. To determine the appropriate level of the port output latches check how the alternate data output is com- bined with the respective port latch output. There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate func- tion mode. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. When using port pins for general purpose output, the initial output value should be written to the port latch prior to enabling the output drivers, in order to avoid undesired transitions on the output pins. This applies to single pins as well as to pin groups (see examples below). SINGLE_BIT: BSET P4.7 ; Initial output level is "high" BSET DP4.7 ; Switch on the output driver BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high" BFLDH DP4, #24H, #24H ; Switch on the output drivers Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by instructions, which do not reference the respective port (see “Particular Pipeline Effects” in Chap- ter 6 - Central Processing Unit (CPU)). 12.2 - PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halves of PORT0 can be written (e.g. via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the correspond- ing direction registers DP0H and DP0L. P0L (FF00h / 80h) SFR Reset Value: - - 00h P0H (FF02h / 81h) SFR Reset Value: - - 00h DP0L (F100h / 80h) ESFR Reset Value: - - 00h 15 14 13 12 11 10 9876543210 -------- P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9876543210 -------- P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 RW RW RW RW RW RW RW RW Bit Function P0X.y Port data register P0H or P0L bit y 15 14 13 12 11 10 9 8 76 543 21 0 - - - - - - - - DP0L.7 DP0L.6 DP0L.5 DP0L.4 DP0L.3 DP0L.2 DP0L.1 DP0L.0 RW RW RW RW RW RW RW RW |
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