ST10F280 datasheet(74/186 Pages) STMICROELECTRONICS

74 / 186 page

ST10F280

74/186

For each feature, a 2-bit control field (ie. 4 bits) is provided for each group of 4 port pads (ie. a port nibble),

in port output control registers POCONx.

POCONx (F0yyh / zzh) for 8-bit Ports

ESFR

Reset Value: - - 00h

POCONx (F0yyh / zzh) for 16-bit Ports

ESFR

Reset Value: 0000h

Note: In case of reading an 8 bit P0CONX register, high Byte ( bit 15..8) is read as 00h.

Port Control Register Allocation

The table below lists the defined POCON registers and the allocation of control bitfields and port pins:

9876543210

--------

PN1DC

PN1EC

PN0DC

PN0EC

9876543210

PN3DC

PN3EC

PN2DC

PN2EC

PN1DC

PN1EC

PN0DC

PN0EC

Bit

Function

PNxEC

Port Nibble x Edge Characteristic (rise/fall time)

Fast edge mode, rise/fall times depend on the driver’s dimensioning.

Slow edge mode, rise/fall times ~60 ns

Reserved

PNxDC

Port Nibble x Driver Characteristic (output current)

High Current mode: Driver always operates with maximum strength.

Dynamic Current mode: Driver strength is reduced after the target level has been reached.

Low Current mode: Driver always operates with reduced strength.

Reserved

Control

Physical

Address

8-Bit

Address

Controlled Port

POCON0L

F080h

40h

P0L.7...4

P0L.3...0

POCON0H

F082h

41h

P0H.7...4

P0H.3...0

POCON1L

F084h

42h

P1L.7...4

P1L.3...0

POCON1H

F086h

43h

P1H.7...4

P1H.3...0

POCON2

F088h

44h

P2.15...12

P2.11...8

P2.7...4

P2.3...0

POCON3

F08Ah

45h

P3.15, P3.13...12

P3.11...8

P3.7...4

P3.3...0

POCON4

F08Ch

46h

P4.7...4

P4.3...0

POCON6

F08Eh

47h

P6.7...4

P6.3...0

POCON7

F090h

48h

P7.7...4

P7.3...0

POCON8

F092h

49h

P8.7...4

P8.3...0

ST10F280 数据表(PDF) 74 Page - STMicroelectronics

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