ST10F280 datasheet(39/186 Pages) STMICROELECTRONICS

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ST10F280

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The System Configuration Register SYSCON

This bit-addressable register provides general system configuration and control functions. The reset

value for register SYSCON depends on the state of the PORT0 pins during reset.

SYSCON (FF12h / 89h)

SFR

Reset Value: 0xx0h

Notes: 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence.

2. Register SYSCON cannot be changed after execution of the EINIT instruction.

6.1 - Multiplier-accumulator Unit (MAC)

The MAC co-processor is a specialized co-pro-

cessor added to the ST10 CPU Core in order to

improve the performances of the ST10 Family in

signal processing algorithms.

Signal processing needs at least three specialized

units operating in parallel to achieve maximum

performance :

– A Multiply-Accumulate Unit,

– An Address Generation Unit, able to feed the

MAC Unit with 2 operands per cycle,

– A Repeat Unit, to execute series of multiply-ac-

cumulate instructions.

The existing ST10 CPU has been modified to

include new addressing capabilities which enable

the CPU to supply the new co-processor with up

to 2 operands per instruction cycle.

This new co-processor (so-called MAC) contains

a fast multiply-accumulate unit and a repeat unit.

The co-processor instructions extend the ST10

CPU instruction set with multiply, multiply-accu-

mulate, 32-bit signed arithmetic operations.

A new transfer instruction CoMOV has also been

added to take benefit of the new addressing capa-

bilities.

9876543210

STKSZ

ROM

SGT

DIS

ROM

BYT

DIS

CLK

CFG

PWD

CFG

OWD

DIS

BDR

STEN

XPEN

VISI

BLE

XPER-

RW1

Bit

Function

XPEN

XBUS Peripheral Enable Bit

Accesses to the on-chip X-Peripherals and their functions are disabled

The on-chip X-Peripherals are enabled and can be accessed.

BDRSTEN

Bidirectional Reset Enable

RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin

RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.

OWDDIS

Oscillator Watchdog Disable Control

Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If

there is no activity on XTAL1 for at least 1

µs, the CPU clock is switched automatically to PLL’s

base frequency (2 to 10MHz).

OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The

PLL is turned off to reduce power supply current..

PWDCFG

Power Down Mode Configuration Control

Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, oth-

erwise the instruction has no effect. To exit Power Down Mode, an external reset must occurs by

asserting the RSTIN pin.

Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast

external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting

one enabled EXxIN pin.

CSCFG

Chip Select Configuration Control

Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE

Unlatched Chip Slect lines : CSx change with rising edge of ALE

ST10F280 数据表(PDF) 39 Page - STMicroelectronics

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