ST10F280 datasheet(57/186 Pages) STMICROELECTRONICS

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ST10F280

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10 - GENERAL PURPOSE TIMER UNIT

The GPT unit is a flexible multifunctional timer/

counter structure which is used for time related

tasks such as event timing and counting, pulse

width

and

duty cycle

measurements, pulse

generation, or pulse multiplication. The GPT unit

contains five 16-bit timers organized into two

separate modules GPT1 and GPT2. Each timer in

each module may operate independently in

several different modes, or may be concatenated

with another timer of the same module.

10.1 - GPT1

Each of the three timers T2, T3, T4 of the GPT1

module can be configured individually for one of

four basic modes of operation: timer, gated timer,

counter

mode

and

incremental

interface

mode.

In timer mode, the input clock for a timer is derived

from the CPU clock, divided by a programmable

prescaler.

In counter mode, the timer is clocked in reference

to external events.

Pulse width or duty cycle measurement is

supported

in gated

timer mode where

the

operation of a timer is controlled by the ‘gate’ level

on an external input pin. For these purposes, each

timer has one associated port pin (TxIN) which

serves as gate or clock input.

Table

lists

the

timer

input

frequencies,

resolution and periods for each pre-scaler option

at 40MHz CPU clock. This also applies to the

Gated Timer Mode of T3 and to the auxiliary

timers T2 and T4 in Timer and Gated Timer Mode.

The count direction (up/down) for each timer is

programmable by software or may be altered

dynamically by an external signal on a port pin

(TxEUD).

In Incremental Interface Mode, the GPT1 timers

(T2, T3, T4) can be directly connected to the

incremental position sensor signals A and B by

their respective inputs TxIN and TxEUD.

Direction and count signals are internally derived

from these two input signals so that the contents

of the respective timer Tx corresponds to the

sensor position. The third position sensor signal

TOP0 can be connected to an interrupt input.

Timer T3 has output toggle latches (TxOTL) which

changes state on each timer over flow / underflow.

The state of this latch may be output on port pins

(TxOUT) for time out monitoring of external

hardware components, or may be used internally

to clock timers T2 and T4 for high resolution of

long duration measurements.

In addition to their basic operating modes, timers

T2 and T4 may be configured as reload or capture

registers for timer T3. When used as capture or

reload registers, timers T2 and T4 are stopped.

The contents of timer T3 is captured into T2 or T4

in response to a signal at their associated input

pins (TxIN).

Timer T3 is reloaded with the contents of T2 or T4

triggered either by an external signal or by a

selectable state transition of its toggle latch

T3OTL. When both T2 and T4 are configured to

alternately reload T3 on opposite state transitions

of T3OTL with the low and high times of a PWM

signal, this signal can be constantly generated

without software intervention.

Table 11 : GPT1 Timer Input Frequencies, Resolution and Periods

fCPU = 40MHz

Timer Input Selection T2I / T3I / T4I

000b

001b

010b

011b

100b

101b

110b

111b

Pre-scaler factor

128

256

512

1024

Input Freq

5MHz

2.5MHz

1.25MHz

625kHz

312.5kHz

156.25kHz

78.125kHz

39.1kHz

Resolution

200ns

400ns

0.8µs

1.6µs

3.2µs

6.4µs

12.8µs

25.6µs

Period maximum

13.1ms

26.2ms

52.4ms

104.8ms

209.7ms

419.4ms

838.9ms

1.678s

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