ST10F280 datasheet(18/186 Pages) STMICROELECTRONICS

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ST10F280

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4 - MEMORY ORGANIZATION

The memory space of the ST10F280 is configured

in a unified memory architecture. Code memory,

data memory, registers and I/O ports are orga-

nized within the same linear address space of

16M Bytes. The entire memory space can be

accessed bytewise or wordwise. Particular por-

tions of the on-chip memory have additionally

been made directly bit addressable.

FLASH: 512K Bytes of on-chip single voltage

FLASH memory.

IRAM:

2K Bytes

on-chip

internal

RAM

(dual-port) is provided as a storage for data, sys-

tem stack, general purpose register banks and

code. The register bank can consist of up to 16

wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) general purpose registers. Base

address is 00’F600h, upper address is 00’FDFFh.

XRAM: 16K Bytes of on-chip extension RAM (sin-

gle port XRAM) is provided as a storage for data,

user stack and code. The XRAM is a single bank,

connected to the internal XBUS and are accessed

like an external memory in 16-bit demultiplexed

bus-mode without waitstate or read/write delay

(50ns access at 40MHz CPU clock). Byte and

word access is allowed.

The XRAM address range is 00’8000h - 00’BFFFh

if enabled (XPEN set bit 2 of SYSCON register-,

and XRAMEN set bit 2 of XPERCON register-). If

bit XRAMEN or XPEN is cleared, then any access

in the address range 00’8000h 00’BFFFh will be

directed to external memory interface, using the

BUSCONx register corresponding to address

matching ADDRSELx register

As the XRAM appears like external memory, it

cannot be used for the ST10F280’s system stack

or register banks. The XRAM is not provided for

single bit storage and therefore is not bit address-

able.

SFR/ESFR: 1024 bytes (2 * 512 bytes) of address

space is reserved for the special function register

areas. SFRs are wordwide registers which are

used for controlling and monitoring functions of

the different on-chip units.

CAN1: Address range 00’EF00h 00’EFFFh is

reserved for the CAN1 Module access. The CAN1

is enabled by setting XPEN bit 2 of the SYSCON

Accesses to the CAN Module use demultiplexed

addresses and a 16-bit data bus (byte accesses

are possible). Two waitstates give an access time

of 100 ns at 40MHz CPU clock. No tristate wait-

state is used.

CAN2: Address range 00’EE00h 00’EEFFh is

reserved for the CAN2 Module access. The CAN2

is enabled by setting XPEN bit 2 of the SYSCON

Accesses to the CAN Module use demultiplexed

addresses and a 16-bit data bus (byte accesses

are possible). Two waitstates give an access time

of 100 ns at 40MHz CPU clock. No tristate wait-

state is used.

In order to meet the needs of designs where more

memory is required than is provided on chip, up to

16M Bytes of external RAM and/or ROM can be

connected to the microcontroller. If one or the two

CAN modules are used, Port 4 can not be pro-

grammed to output all 8 segment address lines.

Thus, only 4 segment address lines can be used,

reducing the external memory space to 5M Bytes

(1M Byte per CS line).

XPWM: Address range 00’EC00h 00’ECFFh is

reserved for the XPWM Module access. The

XPWM is enabled by setting XPEN bit 2 of the

SYSCON register and bit 4 of the new XPERCON

demultiplexed addresses and a 16-bit data bus

(byte accesses are possible). Two waitstates give

an access time of 100 ns at 40MHz CPU clock. No

tristate waitstate is used.

XPORT9, XTIMER, XPORT10, XADCMUX :

Address range 00’C000h 00’C3FFh is reserved

for

the

XPORT9,

XPORT10,

XTIMER

and

XADCMUX peripherals access. The XPORT9,

XTIMER, XPORT10, XADCMUX are enabled by

setting XPEN bit 2 of the SYSCON register and

the bit 3 of the new XPERCON register. Accesses

the

XPORT9,

XTIMER,

XPORT10

and

XADCMUX modules use a 16-bit demultiplexed

bus mode without waitstate or read/write delay

(50ns access at 40MHz CPU clock). Byte and

word access is allowed.

Visibility of XBUS Peripherals

The XBUS peripherals can be separately selected

for being visible to the user by means of corre-

sponding selection bits in the XPERCON register.

If not selected (not activated with XPERCON bit)

before the global enabling with XPEN-bit in

SYSCON register, the corresponding address

space, port pins and interrupts are not occupied

by the peripheral, thus the peripheral is not visible

and not available. SYSCON register is described

in Section 19.2 - System Configuration Registers.

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