ST10F280 datasheet(66/186 Pages) STMICROELECTRONICS

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ST10F280

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11.2.2 - XPWM Module Registers

The XPWM module is controlled via two sets of

registers. The waveforms are selected by the

channel specific registers XPTx (timer), XPPx

(period) and XPWx (pulse width).

Three common registers control the operating

modes and the general functions (XPWMCON0

and XPWMCON1) of the PWM module as well as

the interrupt behavior (XP2IC).

Up/Down Counters XPTx

Each counter XPTx of a PWM channel is clocked

either directly by the CPU clock or by the CPU

clock

divided

64.

Bit

PTIx

XPWMCON0 selects the respective clock source.

A XPWM counter counts up or down (controlled

by hardware), while its respective run control bit

PTRx is set. A timer is started (PTRx = ’1’) via

software and is stopped (PTRx = ’0’) either via

hardware or software, depending on its operating

mode. Control bit PTRx enables or disables the

clock input of counter XPTx rather than controlling

the XPWM output signal.

Note

For the register locations please refer to

the Table 14.

Table 15 summarizes the XPWM frequencies that

result from various combinations of operating

mode, counter resolution (input clock) and pulse

width resolution.

Period Registers XPPx

The 16-bit period register XPPx of a XPWM chan-

nel determines the period of a PWM cycle, i.e. the

frequency of the PWM signal. This register is buff-

ered with a shadow register. The shadow register

is loaded from the respective XPPx register at the

beginning of every new PWM cycle, or upon a

write access to XPPx, while the timer is stopped.

The CPU accesses the XPPx register while the

hardware compares the contents of the shadow

counter XPTx. When a match is found between

counter and XPPx shadow register, the counter is

either reset to 0000h, or the count direction is

switched from counting up to counting down,

depending on the selected operating mode of that

XPWM channel. For the register locations refer to

the Table 14.

Pulse Width Registers XPWx

This 16-bit register holds the actual PWM pulse

width value which corresponds to the duty cycle of

the PWM signal. This register is buffered with a

shadow register. The CPU accesses the XPWx

tents of the shadow register with the contents of

the associated counter XPTx. The shadow regis-

ter is loaded from the respective XPWx register at

the beginning of every new PWM cycle, or upon a

write access to

XPWx, while the timer is

stopped.When the counter value is greater than or

equal to the shadow register value, the PWM sig-

nal is set, otherwise it is reset. The output of the

comparators may be described by the boolean

formula:

PWM output signal = [XPTx]

≥ [XPWx shadow latch].

This type of comparison allows a flexible control of

the PWM signal. For the register locations refer to

theTable 14.

Table 14 : XPWM Module Channel Specific

Address

XPW0

EC30h

XPT0

EC10h

XPW1

EC32h

XPT1

EC12h

XPW2

EC34h

XPT2

EC14h

XPW3

EC36h

XPT3

EC16h

These registers are not

bit-addressable.

XPP0

EC20h

XPP1

EC22h

XPP2

EC24h

XPP3

EC26h

Table 15 : XPWM Frequency

Mode 0

Resolution

8-bit

10-bit

12-bit

14-bit

16-bit

CPU Clock/1

25ns

156.25kHz

39.06kHz

9.77kHz

2.44Hz

610.35Hz

CPU Clock/64

1.6

µs

2.44Hz

610.35Hz

152.58Hz

38.15Hz

9.54Hz

Mode 1

Resolution

8-bit

10-bit

12-bit

14-bit

16-bit

CPU Clock/1

25ns

78.12kHz

19.53kHz

4.88kHz

1.22kHz

305.17Hz

CPU Clock/64

1.6

µs

1.22kHz

305.17Hz

76.29Hz

19.07Hz

4.77Hz

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