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数据搜索系统，热门电子元器件搜索 |
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ST10F280 数据表(PDF) 97 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 186 page  ST10F280 97/186 The port structures of Port 7 differ in the way the output latches are connected to the internal bus and to the pin driver (see the two Figure 47). Pins P7.3...P7.0 (POUT3...POUT0) XOR the alternate data output with the port latch output, which allows to use the alternate data directly or inverted at the pin driver. Figure 46 : Port 7 I/O and Alternate Functions Figure 47 : Block Diagram of Port 7 Pins P7.3...P7.0 Port 7 Alternate Function General Purpose Input/Output P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 CC31IO CC30IO CC29IO CC28IO POUT3 POUT2 POUT1 POUT0 Open Drain Latch Write ODP7.y Read ODP7.y Direction Latch Write DP7.y Read DP7.y MUX 0 1 Input Latch CPU Clock P7.y/POUTy Output Buffer Port Output Latch Read P7.y =1 Port Data Output EXOR Alternate Data Output Write P7.y y = 0...3 |
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