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ST10F280 数据表(PDF) 79 Page - STMicroelectronics |
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ST10F280 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 186 page  ST10F280 79/186 12.3 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (e.g. via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the correspond- ing direction registers DP1H and DP1L. P1L (FF04h / 82h) SFR Reset Value: - - 00h P1H (FF06h / 83h) SFR Reset Value: - - 00h DP1L (F104h / 82h) ESFR Reset Value: - - 00h DP1H (F106h / 83h) ESFR Reset Value: - - 00h 12.3.1 - Alternate Functions of PORT1 When a de-multiplexed external bus is enabled, PORT1 is used as address bus. Note that de-multiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose I/O. The upper four pins of PORT1 (P1H.7...P1H.4) also serve as capture input lines for the CAPCOM2 unit (CC27IO...CC24IO). As all other capture inputs, the capture input func- tion of pins P1H.7...P1H.4 can also be used as external interrupt inputs (200 ns sample rate at 40MHz CPU clock). During external accesses in de-multiplexed bus modes PORT1 outputs the 16-bit intra-segment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a de-multiplexed bus mode, PORT1 is not used and is available for general purpose I/O (see Figure 31). When an external bus mode is enabled, the direc- tion of the port pin and the loading of data into the port output latch are controlled by the bus control- ler hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled “Alternate Data Out- put” via a multiplexer. The alternate data is the 16-bit intra-segment address. 15 14 13 12 11 10 9876543210 -------- P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9876543210 -------- P1H.7 P1H.6 P1H.5 P1H.4 P1L.3 P1H.2 P1H.1 P1H.0 RW RW RW RW RW RW RW RW Bit Function P1X.y Port data register P1H or P1L bit y 15 14 13 12 11 10 9 8 76543210 ----- --- DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0 RW RW RW RW RW RW RW RW 15 14 13 12 11 10 9 8 76543210 ----- --- DP1H.7 DP1H.6DP1H.5DP1H.4DP1H.3DP1H.2 DP1H.1 DP1H.0 RW RW RW RW RW RW RW RW Bit Function DP1X.y Port direction register DP1H or DP1L bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output |
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