ST10F280 datasheet(171/186 Pages) STMICROELECTRONICS

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ST10F280

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20.4.11 - Demultiplexed Bus

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,

ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40MHz CPU clock without wait states).

Table 42 : Demultiplexed Bus Characteristics

Symbol

Parameter

Maximum CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

Minimum

Maximum

Minimum

Maximum

ALE high time

4 + tA

–

TCL - 8.5 + tA

–ns

Address setup to ALE

2 + tA

–

TCL - 10.5 + tA

–ns

t80 CC Address/Unlatched CS setup to

RD, WR

(with RW-delay)

16.5 + 2tA

–

2 TCL - 8.5 + 2tA

–ns

t81 CC Address/Unlatched CS setup to

RD, WR

(no RW-delay)

4 + 2tA

–

TCL - 8.5 + 2tA

–ns

t12 CC RD, WR low time

(with RW-delay)

15.5 + tC

–

2 TCL - 9.5 + tC

–ns

t13 CC RD, WR low time

(no RW-delay)

28 + tC

–

3 TCL - 9.5 + tC

–ns

t14 SR

RD to valid data in

(with RW-delay)

–6 + tC

–

2 TCL - 19 + tC

t15 SR

RD to valid data in

(no RW-delay)

–

18.5 + tC

–

3 TCL - 19 + tC

t16 SR

ALE low to valid data in

–

18.5 + tA +

–

3 TCL - 19

+ tA + tC

t17 SR

Address/Unlatched CS to valid

data in

–22 + 2tA +

–

4 TCL - 28

+ 2tA + tC

t18 SR

Data hold after RD

rising edge

0–

–

t20 SR

Data float after RD rising edge

(with RW-delay)

1 3

–

16.5 + tF

–

2 TCL - 8.5

+ tF + 2tA

t21 SR

Data float after RD rising edge

(no RW-delay)

1 3

–4 + tF

–

TCL - 8.5

+ tF + 2tA

t22 CC Data valid to WR

10 + tC

–

2 TCL - 15 + tC

–ns

t24 CC Data hold after WR

4 + tF

–

TCL - 8.5 + tF

–ns

t26 CC

ALE rising edge after RD, WR

-10 + tF

–

-10 + tF

–ns

t28 CC

Address/Unlatched CS hold

after RD, WR

0 (no tF)

-5 + tF

(tF > 0)

–

0 (no tF)

-5 + tF

(tF > 0)

–ns

t28h CC

Address/Unlatched CS hold

after WRH

-5 + tF

–

-5 + tF

–ns

t38 CC

ALE falling edge to Latched CS

-4 - tA

6 - tA

-4 - tA

6 - tA

t39 SR

Latched CS low to Valid Data In

–

18.5

+ tC + 2tA

–

3 TCL - 19

+ tC + 2tA

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