HD64F2149YV datasheet(324/1075 Pages) RENESAS

324 / 1075 page

Section 10 14-Bit PWM Timer

Rev. 3.00 Jan 18, 2006 page 296 of 1044

REJ09B0280-0300

10.2

10.2.1

PWM (D/A) Counter (DACNT)

R/W

Bit (CPU)

BIT (Counter)

Initial value

Read/Write

R/W

—

REGS

R/W

—

DACNTH

DACNTL

DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The

input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the

DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are

performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details.

DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with

14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the

lower 12 (counter) bits and ignores the upper two (counter) bits.

DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,

subsleep mode, and module stop mode, and by the PWME bit.

Bit 1 of DACNTL (CPU) is not used, and is always read as 1.

DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are

located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS

bit can be accessed regardless of whether DADRB or DACNT is selected.

Bit 0

REGS

Description

DADRA and DADRB can be accessed

DACR and DACNT can be accessed

(Initial value)

HD64F2149YV 数据表(PDF) 324 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 324 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载