HD64F2149YV datasheet(325/1075 Pages) RENESAS

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Section 10 14-Bit PWM Timer

Rev. 3.00 Jan 18, 2006 page 297 of 1044

REJ09B0280-0300

10.2.2

D/A Data Registers A and B (DADRA and DADRB)

DA13

R/W

DA12

R/W

DA11

R/W

DA10

R/W

DA9

R/W

DA6

R/W

DA8

R/W

DA7

R/W

Bit (CPU)

Bit (Data)

DADRA

Initial value

Read/Write

DA5

R/W

DA4

R/W

DA3

R/W

DA2

R/W

DA1

R/W

—

DA0

R/W

—

CFS

R/W

DADRH

DADRL

DA13

R/W

DA12

R/W

DA11

R/W

DA10

R/W

DA9

R/W

DA6

R/W

DA8

R/W

DA7

R/W

DADRB

Initial value

Read/Write

DA5

R/W

DA4

R/W

DA3

R/W

DA2

R/W

DA1

R/W

REGS

R/W

DA0

R/W

CFS

R/W

There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA

corresponds to PWM (D/A) channel A, and DADRB to PWM D/A channel B. The CPU can read

and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,

data transfers between them and the CPU are performed using a temporary register (TEMP). See

section 10.3, Bus Master Interface, for details.

The least significant (CPU) bit of DADRA is not used and is always read as 1.

DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,

subsleep mode, and module stop mode.

Bits 15 to 2—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an

analog value is set in the upper 14 bits of the PWM (D/A) data register.

In each base cycle, the DACNT value is continually compared with these upper 14 bits to

determine the duty cycle of the output waveform, and to decide whether to output a fine-

adjustment pulse equal in width to the resolution. To enable this operation, the data register must

be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is

outside this range, the PWM output is held constant.

A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and

DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data

bits correspond to the two highest counter (DACNT) bits.

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