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HD64F2149YV 数据表(PDF) 322 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 322 Page - Renesas Technology Corp |
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322 / 1075 page  Section 10 14-Bit PWM Timer Rev. 3.00 Jan 18, 2006 page 294 of 1044 REJ09B0280-0300 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the PWM D/A module. Internal clock φ φ/2 PWX0 PWX1 DADRA DADRB DACNT DACR Legend: DACR: PWM D/A control register ( 6 bits) DADRA: PWM D/A data register A (15 bits) DADRB: PWM D/A data register B (15 bits) DACNT: PWM D/A counter (14 bits) Control logic Clock selection Clock Internal data bus Basic cycle compare-match A Fine-adjustment pulse addition A Basic cycle compare-match B Fine-adjustment pulse addition B Basic cycle overflow Comparator A Comparator B Bus interface Module data bus Figure 10.1 PWM D/A Block Diagram |
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