AT89LP51 datasheet(73/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

15. Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig-

gering a system reset when it times out after the software has failed to feed the timer prior to the

timer overflow. By Default the WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and

PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K

clock cycles. The Timer Prescaler can also be used to lengthen the time-out period (see Table

6-2 on page 31) The WDT is disabled by Reset and during Power-down mode. When the WDT

times out without being serviced, an internal RST pulse is generated to reset the CPU. See

Table 15-1 for the available WDT period selections.

Note:

1. The WDT time-out period is dependent on the system clock frequency.

The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the

sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the

WDTEN bit in WDTCON will be set to “1”. To prevent the WDT from generating a reset when if

overflows, the watchdog feed sequence must be written to WDTRST before the end of the time-

out period. To feed the watchdog, two write instructions must be sequentially executed success-

fully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The

instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register.

An incorrect feed or enable sequence will cause an immediate watchdog reset. The program

sequence to feed or enable the watchdog timer is as follows:

MOV WDTRST, #01Eh

MOV WDTRST, #0E1h

15.1

Software Reset

A Software Reset of the AT89LP51/52 is accomplished by writing the software reset sequence

5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software

reset. A normal software reset will set the SWRST flag in WDTCON. However, if at any time an

incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a

software reset will immediately be generated and both the SWRST and WDTOVF flags will be

set. In this manner an intentional software reset may be distinguished from a software error-gen-

erated reset. The program sequence to generate a software reset is as follows:

Table 15-1.

Watchdog Timer Time-out Period Selection

WDT Prescaler Bits

Period(1)

(Clock Cycles)

PS2

PS1

PS0

000

16K

001

32K

010

64K

011

128K

100

256K

101

512K

1024K

111

2048K

Time-out Period

()

System Frequency

--------------------------------------------------

TPS

()

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