AT89LP51 datasheet(34/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that

ensures that the device is reset from system power up. In most cases a RC startup circuit is not

required on the RST pin, reducing system cost, and the RST pin may be left unconnected if a

board-level reset is not present.

Note:

RST also serves as the In-System Programming (ISP) enable. ISP is enabled when the external

reset pin is held active. When ISP is disabled by fuse, ISP may only be entered by pulling RST

active during power-up. If this behavior is necessary, it is recommended to use an active-low reset

so that ISP can be entered by shorting RST to GND at power-up.

Figure 7-3.

Reset Pin Structure

7.4

Watchdog Reset

When the Watchdog times out, it will generate a reset pulse lasting 49 clock cycles. By default

this pulse is also output on the RST pin. To disable the RST output the DISRTO bit in AUXR

(Compatibility mode) or WDTCON (Fast mode) must be set to one. Watchdog reset will set the

WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence

1EH/E1H must be written to WDTRST before the Watchdog times out. See “Programmable

Watchdog Timer” on page 73. for details on the operation of the Watchdog.

7.5

Software Reset

The CPU may generate a 49-clock cycle reset pulse by writing the software reset sequence

5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDTCON. See

“Software Reset” on page 73 for more information on software reset. Writing any sequences

other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and set both

WDTOVF and SWRST to flag an error. Software reset will also drive the RST pin active unless

DISRTO is set.

Power Saving Modes

The AT89LP51/52 supports two different power-reducing modes: Idle and Power-down. These

modes are accessed through the PCON register. Additional steps may be required to achieve

the lowest possible power consumption while using these modes.

8.1

Idle Mode

Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU

state is preserved in its entirety, including the RAM, stack pointer, program counter, program

status word, and accumulator. The Port pins hold the logic states they had at the time that Idle

was activated. Idle mode leaves the peripherals running in order to allow them to wake up the

VCC

DISRTO

WDT Reset

RST

Internal Reset

POL = 1

VCC

DISRTO

WDT Reset

RST

Internal Reset

POL = 0

AT89LP51 数据表(PDF) 34 Page - ATMEL Corporation

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