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AT89LP51 数据表(PDF) 14 Page - ATMEL Corporation |
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AT89LP51 数据表(HTML) 14 Page - ATMEL Corporation |
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14 / 113 page ![]() 14 3709C–MICRO–5/11 AT89LP51/52 - Preliminary access the code memory. The User Signature Array may also be modified by the In-Application Programming interface. When IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access the array (See Section 3.4 on page 23). 3.2 Internal Data Memory The AT89LP51/52 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration. The internal data memory has three address spaces: DATA, IDATA and SFR; as shown in Figure 3-5. Some portions of external data memory are also implemented internally. See “External Data Memory” below for more information. Figure 3-5. Internal Data Memory Map 3.2.1 DATA The first 128 bytes of RAM are directly addressable by an 8-bit address (00H–7FH) included in the instruction. The lowest 32 bytes of DATA memory are grouped into 4 banks of 8 registers each. The RS0 and RS1 bits (PSW.3 and PSW.4) select which register bank is in use. Instruc- tions using register addressing will only access the currently specified bank. The lower 128 bit addresses are also mapped into DATA addresses 20H—2FH. 3.2.2 IDATA The full 256 byte internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1. The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in the IDATA space. 3.2.3 SFR The upper 128 direct addresses (80H–FFH) access the I/O registers. I/O registers on AT89LP devices are referred to as Special Function Registers. The SFRs can only be accessed through direct addressing. All SFR locations are not implemented. See Section 4. for a listed of available SFRs. 3.3 External Data Memory AT89LP microcontrollers support a 16-bit external memory address space for up to 64K bytes of external data memory (XDATA). The external memory space is accessed with the MOVX instructions. Some internal data memory resources are mapped into portions of the external FFH UPPER 128 80H 7FH LOWER 128 0 ACCESSIBLE BY DIRECT ADDRESSING FFH 80H ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING SPECIAL FUNCTION REGISTERS PORTS STATUS AND CONTROL BITS REGISTERS STACK POINTER ACCUMULATOR (ETC.) TIMERS ACCESSIBLE BY INDIRECT ADDRESSING ONLY IDATA SFR DATA/IDATA |
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