AT89LP51 datasheet(38/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

vectored to. The Timer 2 Interrupt is generated by a logic OR of bits TF2 and EXF2 in register

T2CON. Neither of these flags is cleared by hardware when the CPU vectors to the service rou-

tine. The service routine normally must determine whether TF2 or EXF2 generated the interrupt

and that bit must be cleared by software.

The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON. Neither of these

flags is cleared by hardware when the CPU vectors to the service routine. The service routine

normally must determine whether RI or TI generated the interrupt and that bit must be cleared by

software.

All of the bits that generate interrupts can be set or cleared by software, with the same result as

though they had been set or cleared by hardware. That is, interrupts can be generated and

pending interrupts can be canceled in software.

9.1

Interrupt Response Time

The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls

the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the

preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to

the appropriate service routine as the next instruction, provided that the interrupt is not blocked

by any of the following conditions: an interrupt of equal or higher priority level is already in prog-

ress; the instruction in progress is RETI or any write to the IE, IP or IPH registers; the CPU is

currently forced into idle by an IAP or FDATA write. Each of these conditions will block the gen-

eration of the LCALL to the interrupt service routine. The second condition ensures that if the

instruction in progress is RETI or any access to IE, IP or IPH, then at least one more instruction

will be executed before any interrupt is vectored to. The polling cycle is repeated at the last cycle

of each instruction, and the values polled are the values that were present at the previous clock

cycle. If an active interrupt flag is not being serviced because of one of the above conditions and

is no longer active when the blocking condition is removed, the denied interrupt will not be ser-

viced. In other words, the fact that the interrupt flag was once active but not serviced is not

remembered. Every polling cycle is new.

If a request is active and conditions are met for it to be acknowledged, a hardware subroutine

call to the requested service routine will be the next instruction executed. The call itself takes

four cycles. Thus, a minimum of five complete clock cycles elapsed between activation of an

interrupt request and the beginning of execution of the first instruction of the service routine. A

longer response time results if the request is blocked by one of the previously listed conditions. If

an interrupt of equal or higher priority level is already in progress, the additional wait time

depends on the nature of the other interrupt's service routine. If the instruction in progress is not

in its final clock cycle, the additional wait time cannot be more than 4 cycles, since the longest

Table 9-1.

Interrupt Vector Addresses

Interrupt

Source

Vector Address

System Reset

RST or POR or BOD

0000H

External Interrupt 0

IE0

0003H

Timer 0 Overflow

TF0

000BH

External Interrupt 1

IE1

0013H

Timer 1 Overflow

TF1

001BH

Serial Port Interrupt

RI or TI

0023H

Timer 2 Interrupt

TF2 or EXF2

002BH

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