AT89LP51 datasheet(36/113 Pages) ATMEL

36 / 113 page

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

8.2.1

Interrupt Recovery from Power-down

Two external interrupt sources may be configured to terminate Power-down mode: external

interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0 or INT1, that inter-

rupt must be enabled by setting EX0 or EX1 in IE and must be configured for level-sensitive

operation by clearing IT0 or IT1.

When terminating Power-down by an interrupt, two different wake-up modes are available.

When PWDEX in PCON is one, the wake-up period is internally timed as shown in Figure 8-1. At

the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an

internal timer begins counting. The internal clock will not be allowed to propagate to the CPU

until after the timer has timed out. After the time-out period the interrupt service routine will

begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 7-1 on page 33).

The interrupt pin need not remain low for the entire time-out period.

Figure 8-1.

Interrupt Recovery from Power-down (PWDEX = 1)

When PWDEX = “0”, the wake-up period is controlled externally by the interrupt. Again, at the

falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,

the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure 8-

2. The interrupt pin should be held low long enough for the selected clock source to stabilize.

After the rising edge on the pin the interrupt service routine will be executed.

Figure 8-2.

Interrupt Recovery from Power-down (PWDEX = 0)

8.2.2

Reset Recovery from Power-down

The wake-up from Power-down through an external reset is similar to the interrupt with

PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and

an internal timer begins counting as shown in Figure 8-3. The internal clock will not be allowed to

propagate to the CPU until after the timer has timed out. The time-out period is controlled by the

Start-up Timer Fuses. (See Table 7-1 on page 33). If RST returns low before the time-out, a two

clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will

remain in reset until RST is brought low.

PWD

INT1

XTAL1

tSUT

Internal

Clock

PWD

INT1

XTAL1

Internal

Clock

AT89LP51 数据表(PDF) 36 Page - ATMEL Corporation

AT89LP51 数据表(HTML) 36 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载