AT89LP51 datasheet(27/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

• Bit 2 of AUXR1 is hard-wired as a logic 0. The DPS bit may be toggled (to switch data

pointers) simply by incrementing the AUXR1 register, without altering other bits in the register

unintentionally. This is the preferred method when only a single data pointer will be used at

one time.

EX:

INC

AUXR1

; Toggle DPS

•In some cases, both data pointers must be used simultaneously. To prevent frequent toggling

of DPS, the AT89LP51/52 supports a prefix notation for selecting the opposite data pointer

per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed

with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer.

Some assemblers may support this operation by using the /DPTR operand. For example, the

following code performs a block copy within EDATA:

MOV

AUXR1, #00H

; DPS = 0

MOV

DPTR, #SRC

; load source address to dptr0

MOV

/DPTR, #DST

; load destination address to dptr1

MOV

R7, #BLKSIZE

; number of bytes to copy

COPY:

MOVX A, @DPTR

; read source (dptr0)

INC

DPTR

; next src (dptr0+1)

MOVX @/DPTR, A

; write destination (dptr1)

INC

/DPTR

; next dst (dptr1+1)

DJNZ R7, COPY

For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:

EX:

0A5H

INC

DPTR

; equivalent to INC /DPTR

A summary of data pointer instructions with fast context switching is listed inTable 5-1.

5.3.1

Data Pointer Update

The Dual Data Pointers on the AT89LP51/52 include two features that control how the data

pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in AUXR1, configure

the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as

shown in Table 5-2. These bits also control the direction of auto-updates during MOVC and

MOVX.

Table 5-1.

Data Pointer Instructions

Instruction

Operation

DPS = 0

DPS = 1

JMP @A+DPTR

JMP @A+DPTR0

JMP @A+DPTR1

MOV DPTR, #data16

MOV DPTR0, #data16

MOV DPTR1, #data16

MOV /DPTR, #data16

MOV DPTR1, #data16

MOV DPTR0, #data16

INC DPTR

INC DPTR0

INC DPTR1

INC /DPTR

INC DPTR1

INC DPTR0

MOVC A,@A+DPTR

MOVC A,@A+DPTR0

MOVC A,@A+DPTR1

MOVC A,@A+/DPTR

MOVC A,@A+DPTR1

MOVC A,@A+DPTR0

MOVX A,@DPTR

MOVX A,@DPTR0

MOVX A,@DPTR1

MOVX A,@/DPTR

MOVX A,@DPTR1

MOVX A,@DPTR0

MOVX @DPTR, A

MOVX @DPTR0, A

MOVX @DPTR1, A

MOVX @/DPTR, A

MOVX @DPTR1, A

MOVX @DPTR0, A

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