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AT89LP51 数据表(PDF) 39 Page - ATMEL Corporation |
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AT89LP51 数据表(HTML) 39 Page - ATMEL Corporation |
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39 / 113 page  39 3709C–MICRO–5/11 AT89LP51/52 - Preliminary instruction is 5 cycles long. If the instruction in progress is RETI, the additional wait time cannot be more than 9 cycles (a maximum of 4 more cycles to complete the instruction in progress, plus a maximum of 5 cycles to complete the next instruction). Thus, in a single-interrupt system, the response time is always more than 5 clock cycles and less than 14 clock cycles. See Figure 9-1 and Figure 9-2. Figure 9-1. Minimum Interrupt Response Time (Fast Mode) Figure 9-2. Maximum Interrupt Response Time (Fast Mode) Figure 9-3. Minimum Interrupt Response Time (Compatibility Mode) Figure 9-4. Maximum Interrupt Response Time (Compatibility Mode) Clock Cycles INT0 IE0 15 Instruction LCALL 1st ISR Instr. Cur. Instr. Ack. Clock Cycles INT0 IE0 1 14 Instruction RETI MOVX @/DPTR, A LCALL 1st ISR Instr. Ack. 510 Clock Cycles INT0 IE0 1 Instruction LCALL ISR Ack. 14 Clock Cycles INT0 IE0 1 Instruction RETI MUL AB LCALL ISR Ack. 13 37 49 |
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