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AT89LP51 数据表(PDF) 23 Page - ATMEL Corporation

部件名 AT89LP51
功能描述  8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
PDF  113 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT89LP51 数据表(HTML) 23 Page - ATMEL Corporation

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3709C–MICRO–5/11
AT89LP51/52 - Preliminary
3.4
In-Application Programming (IAP)
The AT89LP51/52 supports In-Application Programming (IAP), allowing the program memory to
be modified during execution. IAP can be used to modify the user application on the fly or to use
program memory for nonvolatile data storage. The same page structure write protocol for
FDATA also applies to IAP (See Section 3.3.2.1 “Write Protocol” on page 16). The CPU is
always placed in idle while modifying the program memory. When the write completes, the CPU
will continue executing with the instruction after the MOVX @DPTR,A instruction that started the
write.
To enable access to the program memory, the IAP bit (MEMCON.7) must be set to one and the
IAP User Fuse must be enabled. The IAP User Fuse can disable all IAP operations. When this
fuse is disabled, the IAP bit will be forced to 0. While IAP is enabled, all MOVX @DPTR instruc-
tions will access the CODE space instead of EDATA/FDATA/XDATA. IAP also allows
reprogramming of the User Signature Array when SIGEN = 1. The IAP access settings are sum-
marized in Table 3-4 and Table 3-5.
Note:
When In-Application programming is not required, it is recommended that the IAP User Fuse be
disabled.
Table 3-4.
IAP Access Settings for AT89LP52
IAP
SIGEN
DMEN
MOVX @DPTR
MOVC @DPTR
0
0
0
XDATA (0000–FFFFH)
CODE (0000–1FFFH)
XCODE (2000–FFFFH)
001
FDATA (0000–00FFH)
XDATA (0100–FFFFH)
CODE (0000–1FFFH)
XCODE (2000–FFFFH)
0
1
0
XDATA (0000–FFFFH)
SIG (0000–01FFH)
011
FDATA (0000–00FFH)
XDATA (0100–FFFFH)
SIG (0000–01FFH)
10
X
CODE (0000–1FFFH)
XDATA (2000–FFFFH)
CODE (0000–1FFFH)
XCODE (2000–FFFFH)
11
X
SIG (0000–01FFH)
XDATA (2000–FFFFH)
SIG (0000–01FFH)
Table 3-5.
IAP Access Settings for AT89LP51
IAP
SIGEN
DMEN
MOVX @DPTR
MOVC @DPTR
0
0
0
XDATA (0000–FFFFH)
CODE (0000–0FFFH)
XCODE (1000–FFFFH)
001
FDATA (0000–00FFH)
XDATA (0100–FFFFH)
CODE (0000–0FFFH)
XCODE (1000–FFFFH)
0
1
0
XDATA (0000–FFFFH)
SIG (0000–01FFH)
011
FDATA (0000–00FFH)
XDATA (0100–FFFFH)
SIG (0000–01FFH)
10
X
CODE (0000–0FFFH)
XDATA (1000–FFFFH)
CODE (0000–0FFFH)
XCODE (1000–FFFFH)
11
X
SIG (0000–01FFH)
XDATA (1000–FFFFH)
SIG (0000–01FFH)



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