AT89LP51 datasheet(37/113 Pages) ATMEL

37 / 113 page

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

Figure 8-3.

Reset Recovery from Power-down (POL = 1)

8.3

Reducing Power Consumption

Several possibilities need consideration when trying to reduce the power consumption in an

8051-based system. Generally, Idle or Power-down mode should be used as often as possible.

All unneeded functions should be disabled. The System Clock Divider can scale down the oper-

ating frequency during periods of low demand. The ALE output can be disabled by setting

DISALE in AUXR, thereby also reducing EMI.

Interrupts

The AT89LP51/52 provides 6 interrupt sources: two external interrupts, three timer interrupts,

and a serial port interrupt. These interrupts and the system reset each have a separate program

vector at the start of the program memory space. Each interrupt source can be individually

enabled or disabled by setting or clearing a bit in the interrupt enable register IE. The IE register

also contains a global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or

clearing bits in the interrupt priority registers IP and IPH. IP holds the low order priority bits and

IPH holds the high priority bits for each interrupt. An interrupt service routine in progress can be

interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority.

The highest priority interrupt cannot be interrupted by any other interrupt source. If two requests

of different priority levels are pending at the end of an instruction, the request of higher priority

level is serviced. If requests of the same priority level are pending at the end of an instruction, an

internal polling sequence determines which request is serviced. The polling sequence is based

on the vector address; an interrupt with a lower vector address has higher priority than an inter-

rupt with a higher vector address. Note that the polling sequence is only used to resolve pending

requests of the same priority level.

The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,

depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-

rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears

the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-

rupt was level activated, then the external requesting source (rather than the on-chip hardware)

controls the request flag.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in

their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is

generated, the on-chip hardware clears the flag that generated it when the service routine is

PWD

RST

XTAL1

tSUT

Internal

Clock

Internal

Reset

AT89LP51 数据表(PDF) 37 Page - ATMEL Corporation

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