AT89LP51 datasheet(87/113 Pages) ATMEL

87 / 113 page

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

Notes:

1. The default state for Tristate Ports is 00h. All other fuses default to FFh.

2. Changes to these fuses will only take effect after a device POR.

3. Changes to these fuses will only take effect after the ISP session terminates by bringing RST inactive.

17.8

User Signature

The User Signature Array contains 256 bytes of non-volatile memory in two 128-byte pages. The

User Signature is available for serial numbers, firmware revision information, date codes or other

user parameters. The User Signature Array may only be written by an external device when the

User Signature Programming Fuse is enabled. When the fuse is enabled, Chip Erase will also

erase the first page of the array. When the fuse is disabled, the array is not affected by write or

erase commands. Programming of the Signature Array can also be disabled by the Lock Bits.

However, reading the signature is always allowed and the array should not be used to store

security sensitive information. The User Signature Array may be modified during execution

through the In-Application Programming interface, regardless of the state of the User Signature

Programming fuse or Lock Bits, provided that the IAP Fuse is enabled. Note that the address of

the User Signature Array, as seen by the IAP interface, equals the User Signature address plus

256 (0100H–01FFH instead of 0000H–00FFH).

17.9

Programming Interface Timing

This section details general system timing sequences and constraints for entering or exiting In-

System Programming as well as parameters related to the Serial Peripheral Interface during

ISP. The general timing parameters for the following waveform figures are listed in section “Tim-

ing Parameters” on page 91.

17.9.1

Power-up Sequence

Execute this sequence to enter programming mode immediately after power-up. In the RST pin

is disabled or if the ISP Fuse is disabled, this is the only method to enter programming (see

“External Reset” on page 33).

Apply power between VDD and GND pins. RST should remain low.

Wait at least t

PWRUP. and drive RST high if active-high otherwise keep low.

Wait at least t

SUT for the internal Power-on Reset to complete. The value of tSUT will

depend on the current settings of the device.

Start programming session.

07H

Tristate Ports

FFh: I/O Ports start in input-only mode (tristated) after reset

00h: I/O Ports start in quasi-bidirectional mode after reset

08H

In-Application Programming

FFh: In-Application Programming Disabled

00h: In-Application Programming Enabled

09H

R1 Enable

FFh: 5 M

Ω resistor on XTAL1 Disabled

00h: 5 M

Ω resistor on XTAL1 Enabled

Table 17-5.

User Configuration Fuse Definitions

Address

Fuse Name

Description

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