AT89LP51 datasheet(18/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

to the page buffer before starting the auto-erase sequence. The stored value of the high half

page must be written without auto-erase after the programming of the low half page completes.

This method reduces the amount of RAM required; however, more software overhead is needed

because the read-and-load-back routine must skip those bytes in the page that need to be

updated in order to prevent those locations in the buffer from being loaded with the previous

data, as this will block the new data from being loaded correctly.

A write sequence will not occur if the Brown-out Detector is active. If a write currently in progress

is interrupted by the BOD due to a low voltage condition, the ERR flag will be set.

3.3.3

External Data Memory Interface

The AT89LP51/52 uses the standard 8051 external data memory interface with the upper

address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE, RD

and WR strobes. The interface may be used in two different configurations depending on which

type of MOVX instruction is used to access XDATA.

Figure 3-10 shows a hardware configuration for accessing up to 64K bytes of external RAM

using a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the RAM. The

Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-

ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte

throughout the operation. The MOVX @DPTR instructions use Linear Address mode.

Table 3-2.

MEMCON

– Memory Control Register

MEMCON = 96H

Reset Value = 0000 0XXXB

Not Bit Addressable

IAP

AERS

LDPG

MWEN

DMEN

ERR

BUSY

WRTINH

Bit

543

Symbol

Function

IAP

In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space

is enabled and MOVX @DPTR instructions will access CODE/SIG instead of EDATA or FDATA. Clear IAP to disable

programming of CODE/SIG and allow access to EDATA and FDATA.

AERS

Auto-Erase Enable. Set to perform an auto-erase of a Flash memory page (CODE, SIG or FDATA) during the next write

sequence. Clear to perform write without erase.

LDPG

Load Page Enable. Set to this bit to load multiple bytes to the temporary page buffer. Byte locations may not be loaded

more than once before a write. LDPG must be cleared before writing.

MWEN

Memory Write Enable. Set to enable programming of a nonvolatile memory location (CODE, SIG or FDATA). Clear to

disable programming of all nonvolatile memories.

DMEN

Data Memory Enable. Set to enable nonvolatile data memory and map it into the FDATA space. Clear to disable

nonvolatile data memory.

ERR

Error Flag. Set by hardware if an error occurred during the last programming sequence due to a brownout condition (low

voltage on VDD). Must be cleared by software.

BUSY

Busy Flag.

WRTINH

Write Inhibit Flag. Cleared by hardware when the voltage on VDD has fallen below the minimum programming voltage.

Set by hardware when the voltage on VDD is above the minimum programming voltage.

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