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AT89LP51 数据表(PDF) 98 Page - ATMEL Corporation |
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AT89LP51 数据表(HTML) 98 Page - ATMEL Corporation |
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98 / 113 page  98 3709C–MICRO–5/11 AT89LP51/52 - Preliminary 18.6 External Memory Characteristics The values shown in this table are valid for T A = -40°C to 85°C and VDD = 2.4 to 5.5V, unless otherwise noted. Under oper- ating conditions, load capacitance for Port 0, ALE and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. Parameters refer to Figure 18-6, Figure 18-7 and Figure 18-8. Notes:1. Compatibility Mode timing for MOVX also applies to Fast Mode during exeternal execution of MOVX. 2. This assumes 50% clock duty cycle. The half period depends on the clock high value t CHCX (high duty cycle). 3. This assumes 50% clock duty cycle. The half period depends on the clock low value tCLCX (low duty cycle). 4. In some cases parameter tLHLL may have a minimum of 0.5tCLCL during Fast mode external execution with DISALE = 0. 5. The strobe pulse width may be lengthened by 1, 2 or 3 additional t CLCL using wait states. Table 18-4. External Program and Data Memory Characteristics Symbol Parameter Compatibility Mode(1) Fast Mode(1) Units Min Max Min Max 1/t CLCL Oscillator Frequency 0 24024 MHz t LHLL ALE Pulse Width t CLCL - d t CLCL - d (4) ns t AVLL Address Valid to ALE Low 0.5t CLCL - d (2) 0.5t CLCL - d (2) ns t LLAX Address Hold after ALE Low 0.5t CLCL - d (3) 0.5t CLCL - d (3) ns t LLIV ALE Low to Valid Instruction In 2t CLCL - d 2t CLCL - d ns t LLPL ALE Low to PSEN Low 0.5t CLCL - d (2) 0.5t CLCL - d (2) ns t PLPH PSEN Pulse WIdth 1.5t CLCL - d (2) 1.5t CLCL - d (2) ns t PLIV PSEN Low to Valid Instruction In 1.5t CLCL - d (2) 1.5t CLCL - d (2) ns t PXIX Input Instruction Hold after PSEN 00 ns t PXIZ Input Instruction Float after PSEN 0.5t CLCL - d (2) 0.5t CLCL - d (2) ns t PXAV PSEN to Address Valid 0.5t CLCL - d (2) 0.5t CLCL - d (2) ns t AVIV Address to Valid Instruction In 2.5t CLCL - d (2) 2.5t CLCL - d (2) ns t PLAZ PSEN Low to Address Float10 10 ns t RLRH RD Pulse Width (5) 3t CLCL - d t CLCL - d ns t WLWH WR Pulse Width(5) 3t CLCL - d t CLCL - d ns t RLDV RD Low to Valid Data In 2.5t CLCL - d t CLCL - d ns t RHDX Data Hold after RD 00 ns t RHDZ Data Float after RD t CLCL - d t CLCL - d ns t LLDV ALE Low to Valid Data In 4t CLCL - d 2t CLCL - d ns t AVDV Address to Valid Data In 4.5t CLCL - d (2) 2.5t CLCL - d (2) ns t LLWL ALE Low to RD or WR Low 1.5t CLCL - d 1.5t CLCL + d t CLCL - d t CLCL + d ns t AVWL Address to RD or WR Low 2t CLCL - d (2) 1.5t CLCL - d (2) ns t QVWX Data Valid to WR Transition 1t CLCL - d (2) 0.5t CLCL - d (2) ns t QVWH Data Valid to WR High 4t CLCL - d (2) 1.5t CLCL - d (2) ns t WHQX Data Hold after WR 1t CLCL - d (3) 0.5t CLCL - d (3) ns t RLAZ RD Low to Address Float-1t CLCL + d (2) -0.5t CLCL + d (2) ns t WHAX Address Hold after RD or WR High 1t CLCL - d (3) 0.5t CLCL - d (3) ns t WHLH RD or WR High to ALE High 0.5t CLCL - d 0.5t CLCL + d t CLCL - d ns |
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