AT89LP51 datasheet(32/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

Reset

During reset, all I/O Registers are set to their initial values, the port pins are set to their default

mode, and the program starts execution from the Reset Vector, 0000H. The AT89LP51/52 has

five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and soft-

ware reset.

7.1

Power-on Reset

A Power-on Reset (POR) is generated by an on-chip detection circuit. The detection level V

POR

is nominally 1.4V. The POR is activated whenever V

DD is below the detection level. The POR cir-

cuit can be used to trigger the start-up reset or to detect a major supply voltage failure. The POR

circuit ensures that the device is reset from power-on. A power-on sequence is shown in Figure

7-1. When V

DD reaches the Power-on Reset threshold voltage VPOR, an initialization sequence

lasting t

POR is started. When the initialization sequence completes, the start-up timer determines

how long the device is kept in POR after V

DD rise. The start-up timer does not begin counting

until after V

DD reaches the Brown-out Detector (BOD) threshold voltage VBOD. The POR signal is

activated again, without any delay, when V

DD falls below the POR threshold level. A Power-on

Reset (i.e. a cold reset) will set the POF flag in PCON. The internally generated reset can be

extended beyond the power-on period by holding the RST pin active longer than the time-out.

Figure 7-1.

Power-on Reset Sequence

Note:

POR is approximately 143 µs ± 5%.

The start-up timer delay is user-configurable with the Start-up Time User Fuses and depends on

the clock source (Table 7-1). The Start-Up Time fuses also control the length of the start-up time

after a Brown-out Reset or when waking up from Power-down during internally timed mode. The

start-up delay should be selected to provide enough settling time for V

DD and the selected clock

source. The device operating environment (supply voltage, frequency, temperature, etc.) must

meet the minimum system requirements before the device exits reset and starts normal opera-

tion. The RST pin may be held active externally until these conditions are met.

VDD

RST

Time-out

POR

RHD

POR

Internal

Reset

RST

Internal

Reset

SUT

BOD

(RST Tied to GND)

(RST Controlled Externally)

POL

(POL Tied to VCC)

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