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AT89LP51 数据表(PDF) 91 Page - ATMEL Corporation

部件名 AT89LP51
功能描述  8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash
PDF  113 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT89LP51 数据表(HTML) 91 Page - ATMEL Corporation

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3709C–MICRO–5/11
AT89LP51/52 - Preliminary
17.9.6
Timing Parameters
The timing parameters for Figure 17-9, Figure 17-10, Figure 17-11, Figure 17-12, Figure 17-14
and Figure 17-15 are shown in Table .
Note:
1. t
SCK is independent of tCLCL.
Table 17-6.
Programming Interface Timing Parameters
Symbol
Parameter
Min
Max
Units
t
CLCL
System Clock Cycle Time
0
60
ns
tPWRUP
Power On to SS High Time
10
µs
tPOR
Power-on Reset Time
100
µs
t
PWRDN
SS Tristate to Power Off
1
µs
tRLZ
RST Low to I/O Tristate
tCLCL
2 tCLCL
ns
tSTL
RST Low Settling Time
100
ns
t
RHZ
RST High to SS Tristate
0
2 t
CLCL
ns
tSCK
Serial Clock Cycle Time
200(1)
ns
tSHSL
Clock High Time
75
ns
t
SLSH
Clock Low Time
50
ns
tSR
Rise Time
25
ns
tSF
Fall Time
25
ns
t
SIS
Serial Input Setup Time
10
ns
tSIH
Serial Input Hold Time
10
ns
t
SOH
Serial Output Hold Time
10
ns
t
SOV
Serial Output Valid Time
35
ns
tPIS
Parallel Input Setup Time
10
ns
t
PIH
Parallel Input Hold Time
10
ns
t
POH
Parallel Output Hold Time
10
ns
tPOV
Parallel Output Valid Time
35
ns
t
SOE
Serial Output Enable Time
10
ns
t
SOX
Serial Output Disable Time
25
ns
tPOE
Parallel Output Enable Time
10
ns
t
POX
Parallel Output Disable Time
25
ns
t
SSE
RST Active Lead Time
t
SLSH
ns
tSSD
RST Inactive Lag Time
tSLSH
ns
t
ZSS
SCK Setup to SS Low
25
ns
t
SSZ
SCK Hold after SS High
25
ns
tWR
Write Cycle Time
2.5
ms
t
AWR
Write Cycle with Auto-Erase Time
5
ms
tERS
Chip Erase Cycle Time
7.5
ms



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