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AT89LP51 数据表(PDF) 26 Page - ATMEL Corporation |
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AT89LP51 数据表(HTML) 26 Page - ATMEL Corporation |
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26 / 113 page  26 3709C–MICRO–5/11 AT89LP51/52 - Preliminary 5.2 Compatibility Mode Compatibility (12-Clock) mode is enabled by default from the factory or by setting the Compati- bility User Fuse. In Compatibility mode instruction bytes are fetched every three system clock cycles and the CPU operates with 6-state machine cycles and a divide-by-2 system clock for 12 oscillator periods per machine cycle. Standard instructions execute in1, 2 or 4 machine cycles. Instruction timing in this mode is compatible with standard 8051s such as the AT89S51/52. Compatibility mode can be used to preserve the execution profiles of legacy applications. For a summary of differences between Fast and Compatibility modes see Table 2-3 on page 10. Examples of Compatibility mode instructions are shown in Figure 5-2. Figure 5-2. Instruction Execution Sequences in Compatibility Mode 5.3 Enhanced Dual Data Pointers The AT89LP51/52 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H and 85H). The data pointers are used by several instructions to access the program or data memo- ries. The Data Pointer Configuration Register (AUXR1) controls operation of the dual data pointers (Table 5-3 on page 28). The DPS bit in AUXR1 selects which data pointer is currently referenced by instructions including the DPTR operand. Each data pointer may be accessed at its respective SFR addresses regardless of the DPS value. The AT89LP51/52 provides two methods for fast context switching of the data pointers: S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 CLK CLK ALE ALE READ OPCODE READ OPCODE (A) 1-byte, 1-cycle instruction, e.g., INC A A (B) 2-byte, 1-cycle instruction, e.g., ADD A, #data (B) 2-byte, 1-cycle instruction, e.g., ADD A, #data (C) 1-byte, 2-cycle instruction, e.g., INC DPTR (C) 1-byte, 2-cycle instruction, e.g., INC DPTR (D) MOVX (1-byte, 2-cycle) (D) MOVX (1-byte, 2-cycle) READ NEXT READ NEXT OPCODE OPCODE (DISCARD) (DISCARD) READ NEXT OPCODE AGAIN READ NEXT OPCODE AGAIN READ OPCODE READ OPCODE READ 2ND READ 2ND BYTE BYTE READ NEXT OPCODE READ NEXT OPCODE READ OPCODE READ OPCODE READ NEXT READ NEXT OPCODE AGAIN OPCODE AGAIN READ READ OPCODE OPCODE (MOVX) (MOVX) NO NO ALE ALE READ NEXT READ NEXT OPCODE (DISCARD) OPCODE (DISCARD) READ NEXT READ NEXT OPCODE OPCODE AGAIN AGAIN NO NO FETCH FETCH DA DATA ACCESS EXTERNAL MEMOR ACCESS EXTERNAL MEMORY ADDR ADDR NO NO FETCH FETCH READ NEXT READ NEXT OPCODE (DISCARD) OPCODE (DISCARD) |
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