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AT89LP51 数据表(PDF) 45 Page - ATMEL Corporation |
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AT89LP51 数据表(HTML) 45 Page - ATMEL Corporation |
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45 / 113 page  45 3709C–MICRO–5/11 AT89LP51/52 - Preliminary 10.3 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP51/52 share functionality with the various I/Os needed for the peripheral units. Table 10-6 lists the alternate functions of the port pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwisethe input/output will always be “0”. However, alternate functions may be temporarily forced to “0” by clearing the associated port bit, provided that the pin is not in input-only mode. Furthermore, each pin must be configured for the correct input/output mode as required by its peripheral before it may be used as such. Table 10-5 shows how to configure a generic pin for use with an alternate function. If two or more port pins on the same 8-bit require difference direc- tions, the port must be configured for bidirectional operation. Table 10-5. Pin Function Configurations for Port x Pin y PxM0 PxM1 Px.y I/O Mode 00 1 bidirectional (internal pull-up) 01 1 output 10 X input 11 1 bidirectional (external pull-up) Table 10-6. Port Pin Alternate Functions Port Pin Configuration Bits Alternate Function Notes PxM0 PxM1 P0.0–P0.7 N/A AD0–AD7 Address and data on Port 0 are automatically configured as output or input regardless of P0M0 and P0M1. P1.0 P1M0 P1M1 T2 T2 Clock out toggles P1.0 directly P1.1 P1M0 P1M1 T2EX P1.5 P1M0 P1M1 MOSI P1.6 P1M0 P1M1 MISO P1.7 P1M0 P1M1 SCK P2.0–P2.7 N/A A8–A15 Address on Port 2 is automatically configured as output regardless of P2M0 and P2M1. P3.0 P3M0 P3M1 RXD P3.1 P3M0 P3M1 TXD P3.2 P3M0 P3M1 INT0 P3.3 P3M0 P3M1 INT1 P3.4 P3M0 P3M1 T0 T0 Clock out toggles P3.4 directly P3.5 P3M0 P3M1 T1 T1 Clock out toggles P3.5 directly P3.6 P3M0 P3M1 WR P3.7 P3M0 P3M1 RD |
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