AT89LP51 datasheet(43/113 Pages) ATMEL

43 / 113 page

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

Figure 10-1. Quasi-bidirectional Output

Figure 10-2. Input Only

Figure 10-3. Input Circuit for P3.2, P3.3, P4.6 and P4.7

10.1.3

Open-drain Output

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor

of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-

figured in this manner must have an external pull-up, typically a resistor tied to V

DD. The pull-

down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-

ration is shown in Figure 10-4. The input circuitry of P3.2, P3.3, P4.6 and P4.7 is not disabled

during Power-down (see Figure 10-3) and therefore these pins should not be left floating during

Power-down when configured in this mode.

Figure 10-4. Open-Drain Output

1 Clock Delay

(D Flip-Flop)

Strong

Very

Weak

Port

VCC

From Port

Input

Data

PWD

Port

Input

Data

PWD

Port

Input

Data

Port

From Port

Input

Data

PWD

AT89LP51 数据表(PDF) 43 Page - ATMEL Corporation

AT89LP51 数据表(HTML) 43 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AT89LP51 数据表(PDF) 43 Page - ATMEL Corporation

AT89LP51 数据表(HTML) 43 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载