AT89LP51 datasheet(74/113 Pages) ATMEL

74 / 113 page

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

MOV WDTRST, #05Ah

MOV WDTRST, #0A5h

Note:

1. WDTCON.4 and WDTCON.3 function as WDIDLE and DISRTO only in Fast mode. In Compatibility mode these bits are in

AUXR. (See Table 3-3 on page 20)

Table 15-2.

WDTCON – Watchdog Control Register

WDTCON Address = A7H

Reset Value = 0000 0XX0B

Not Bit Addressable

PS2PS1PS0

WDIDLE(1)

DISRTO(1)

SWRST

WDTOVF

WDTEN

Bit

654

321

Symbol

Function

PS2

PS1

PS0

Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal

period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.

WDIDLE

WDT Disable during Idle(1). When WDIDLE = 0 the WDT continues to count in Idle mode. When WDIDLE = 1 the WDT

halts counting in Idle mode.

DISRTO

Disable Reset Output(1). When DISTRO = 0 the reset pin is driven to the same level as POL when the WDT resets.

When DISRTO = 1 the reset pin is input only.

SWRST

Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set

when an incorrect sequence is written to WDTRST. Must be cleared by software.

WDTOVF

Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect

sequence is written to WDTRST. Must be cleared by software.

WDTEN

Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The

WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST

Table 15-3.

WDTRST – Watchdog Reset Register

WDTCON Address = A6H

(Write-Only)

Not Bit Addressable

–

–––

––

Bit

654

321

The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading

the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to

WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST.

AT89LP51 数据表(PDF) 74 Page - ATMEL Corporation

AT89LP51 数据表(HTML) 74 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载