AT89LP51 datasheet(100/113 Pages) ATMEL

100 / 113 page

100

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

Figure 18-9. Shift Register Mode Timing Waveform

18.8

Test Conditions

18.8.1

AC Testing Input/Output Waveform

(1)

Note:

1. AC Inputs during testing are driven at VDD - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at

VIH min. for a logic “1” and VIL max. for a logic “0”.

18.7

Serial Port Timing: Shift Register Mode

The values in this table are valid for V

DD = 2.4V to 5.5V and Load Capacitance = 80 pF.

Symbol

Parameter

SMOD1 = 0

SMOD1 = 1

Units

Min

Max

Min

Max

XLXL

Serial Port Clock Cycle Time

CLCL -15

µs

tQVXH

Output Data Setup to Clock Rising Edge

3tCLCL -15

tCLCL -15

XHQX

Output Data Hold after Clock Rising Edge

CLCL -15

tXHDX

Input Data Hold after Clock Rising Edge

tXHDV

Input Data Valid to Clock Rising Edge

Valid

Clock

Write to SBUF

Output Data

Clear RI

Input Data

SMOD1 = 0

Valid

Clock

Write to SBUF

Output Data

Clear RI

Input Data

SMOD1 = 1

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