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AT89LP51 数据表(PDF) 41 Page - ATMEL Corporation |
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AT89LP51 数据表(HTML) 41 Page - ATMEL Corporation |
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41 / 113 page ![]() 41 3709C–MICRO–5/11 AT89LP51/52 - Preliminary 10. I/O Ports The AT89LP51/52 can be configured for between 32 and 36 I/O pins. The exact number of I/O pins available depends on the clock, external memory and package type as shown in Table 10- 1. 10.1 Port Configuration Each 8-bit port on the AT89LP51/52 may be configured in one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may be assigned in software on a port-by-port basis as shown in Table 10-2 using the PMOD register listed in Table 10-3. The Tristate-Port User Fuse determines the default state of the port pins (See “User Configuration Fuses” on page 86). When the fuse is enabled, all port pins default to input-only mode after reset. When the fuse is disabled, all port pins on P1, P2 and P3 default to quasi-bidirectional mode after reset and are weakly pulled high. P0 is set to Open-drain mode. P4 always operates in quasi-bidirectional mode. Each port pin also has a Schmitt-triggered input for improved input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled with the exception of P3.2 (INT0), P3.3 (INT1), RST, P4.6 (XTAL1) and P4.7 (XTAL2). Therefore, P3.2, P3.3, P4.6 and P4.7 should not be left floating during Power-down. . Table 10-1. I/O Pin Configurations Clock Source External Program Access External Data Access Number of I/O Pins External Crystal or Resonator Yes (PSEN+ALE+P0+P2) Yes (RD+WR) 14 No 16 No Yes (ALE+RD+WR+P0) 31 No 34 External Clock Yes (PSEN+ALE+P0+P2) Yes (RD+WR) 15 No 17 No Yes (ALE+RD+WR+P0) 32 No 35 Internal RC Oscillator Yes (PSEN+ALE+P0+P2) Yes (RD+WR) 16 No 18 No Yes (ALE+RD+WR+P0) 33 No 36 Table 10-2. Configuration Modes for Port x PxM0 PxM1 Port Mode 00 Quasi-bidirectional 01 Push-pull Output 10 Input Only (High Impedance) 1 1 Open-Drain Output |
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