AT89LP51 datasheet(46/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

11. Timer 0 and Timer 1

The AT89LP51/52 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following

features:

• Two independent 16-bit timer/counters with 8-bit reload registers

•UART baud rate generation using Timer 1

•Output pin toggle on timer overflow

• Split timer mode allows for three separate timers (2 8-bit, 1 16-bit)

•Gated modes allow timers to run/halt based on an external input

Timer 0 and Timer 1 have similar modes of operation. As timers, the timer registers normally

increase every clock cycle. Thus, the registers count clock cycles. The timer rate can be pres-

caled by a value between 1 and 16 using the Timer Prescaler (see Table 6-2 on page 31). Both

Timers share the same prescaler. In Compatibility mode CDV defaults to 2, so a clock cycle con-

sists of two oscillator periods,and the prescaler defaults to 6 making the count rate equal to 1/12

of the oscillator frequency. By default in Fast mode CDV = 0 and TPS =0 so the count rate is

equal to the oscillator frequency.

As counters, the timer registers are incremented in response to a 1-to-0 transition at the corre-

sponding input pins, T0 or T1. In Fast mode the external input is sampled every clock cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is incre-

mented. The new count value appears in the register during the cycle following the one in which

the transition was detected. Since 2 clock cycles are required to recognize a 1-to-0 transition,

the maximum count rate is 1/2 of the system frequency. There are no restrictions on the duty

cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a

given level is sampled at least once before it changes.

In Compatibility mode the counter input sampling is controlled by the prescaler. Since TPS

defaults to 6 in this mode, the pins are sampled every six system clocks. Therefore the input sig-

nal should be held for at least six clock cycles to ensure that a given level is sampled at least

once before it changes.

Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:

13-bit timer, 16-bit timer, 8-bit auto-reload timer, and split timer. The control bits C/T in the Spe-

cial Function Register TMOD select the Timer or Counter function. The bit pairs (M1, M0) in

TMOD select the operating modes.

Table 11-1.

Timer 0/1 Register Summary

Name

Address

Purpose

Bit-Addressable

TCON

88H

Control

TMOD

89H

Mode

TL0

8AH

Timer 0 low-byte

TL1

8BH

Timer 1 low-byte

TH0

8CH

Timer 0 high-byte

TH1

8DH

Timer 1 high-byte

TCONB

91H

Mode

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