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TNETX15VE 数据表(PDF) 21 Page - Texas Instruments |
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TNETX15VE 数据表(HTML) 21 Page - Texas Instruments |
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21 / 113 page ![]() TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 internal register descriptions revision register, revision at 0x00 (DIO) MOST-SIGNIFICANT BIT BIT LEAST-SIGNIFICANT BIT 7 6 5 4 3 2 1 0 Product Code Revision Initial Values After Reset 0 0 1 0 0 0 0 0 This register contains the revision code for the device. The initial revision code is hardwired to 0x20, which indicates the version 2.0 device. This register is read only, and writes to it are ignored. SRAM size-select register, RAMsize at 0x01 (DIO) The RAMsize register can be written to only when the START bit in the control register is set to 0. This register is automatically loaded from the EEPROM when the RESET terminal is asserted low, when DIO address high register contains 0x40, or when LOAD in the control register is set. BIT 7 6 5 4 3 2 1 0 Reserved RSIZE Initial Values After Reset 0 0 0 0 0 0 0 0 BIT NAME FUNCTION 7–4 Reserved Writes to this location are ignored and are read as 0. 3–0 RSIZE Ram size select. This field indicates the size of the external SRAM, and has a bearing on the number of addresses that the TNETX15VE supports. The TNETX15VE uses this field to determine how many tables to initialize as part of the reset sequence by indicating how many address lines to use. All the intermediate pointers used for address decode are stored in external SRAM, which means external SRAM is required. The end points of an address lookup are stored in the internal RAM for speed. The internal SRAM is used also for the one-address/port FIFO, and the 32-location FIFO used to record source addresses for frames that override the receive block (spanning-tree BPDU support). This field is written only when the START bit is 0. This field also is loaded from the EEPROM interface during auto-load. Code values are as follows: RAMsize REGISTER 640 × 16 RAM SIZE WORST CASE 0x00 832 × 16 2 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D to 0x0F 1K × 16 2K × 16 4K × 16 8K × 16 16K × 16 32K × 16 64K × 16 128K × 16 256K × 16 512K × 16 1M × 16 Reserved 2 3 7 14 28 59 123 251 507 1019 1954 1954 Caution should be taken not to specify more RAM than is actually present. The state machines allocating space treat this value literally. Unusual effects concerning addresses can be observed if this space is smaller than indicated. For instance, addresses can appear more than once with the first few bits changed to 1s. |
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